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CP3SP33SMS/NOPB Datasheet(PDF) 119 Page - Texas Instruments |
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CP3SP33SMS/NOPB Datasheet(HTML) 119 Page - Texas Instruments |
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119 / 407 page  SLE SCLK SDAT DS012 D0 D14 D15 A0 A1 A2 A3 A4 W H0 H1 H2 CP3SP33 www.ti.com SNOSCW5 – MAY 2013 Data is transferred on the serial interface with the most significant bit (MSB) first. Write Operation When the R/W bit is clear, the 16 bits of the data field are shifted out of the CP3SP33 on the falling edge of SCLK. Data is sampled by the radio chip on the rising edge of SCLK. When SLE is high, the 16-bit data are copied into the radio chip register on the next rising edge of SCLK. The data is loaded in the appropriate radio chip register depending on the state of the four address bits, Address[4:0]. Figure 19-4 shows the timing for the write operation. Figure 19-4. Serial Interface Write Timing Copyright © 2013, Texas Instruments Incorporated Bluetooth Controller 119 Submit Documentation Feedback Product Folder Links :CP3SP33 |
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