CP3SP33SMSSLASHNOPB datasheet(117/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

19.1.1 RF Interface Signals

The RF interface signals are grouped as follows:

•

Modem Signals (CLKIN, RFDATA, and RFSYNC)

•

Control Signal (RFCE)

•

Serial Interface Signals (SCLK, SDAT, and SLE)

•

Bluetooth Sequencer Status Signals (BTSEQ1, BTSEQ2, and BTSEQ2)

Software must enable the alternate functions of the RF interface signals to allow them to be controlled by

the Bluetooth module.

19.1.1.1 CLKIN

The CLKIN pin is the input signal for the 12-MHz clock signal. The radio chip uses this signal internally as

the 12× oversampling clock and provides it externally to the CP3SP33 for use as the Main Clock.

19.1.1.2 RFDATA

The RFDATA signal is the multiplexed Bluetooth data receive and transmit signal. The data is provided at

a bit rate of 1 Mbit/s with 12× oversampling, synchronized to the 12 MHz CLKIN. The RFDATA signal is a

dedicated RF interface pin. This signal is driven to a logic high level after reset.

19.1.1.3 RFSYNC

In receive mode (data direction from the radio chip to the CP3SP33), the RFSYNC signal acts as the

frequency correction/DC compensation circuit control output to the radio chip. The RFSYNC signal is

driven low throughout the correlation phase and driven high when synchronization to the received access

code is achieved.

In transmit mode (data direction from the CP3SP33 to the radio chip), the RFSYNC signal enables the RF

output of the radio chip. When the RFSYNC pin is driven high, the RF transmitter circuit of the radio chip

is enabled, corresponding to the settings of the power control register in the radio chip

The RFSYNC signal is the alternate function of the general-purpose I/O pin PG0. At reset, this pin is in

TRI-STATE mode. Software must enable the alternate function of the PG0 pin to give control over this

signal to the RF interface.

19.1.1.4 RFCE

The RFCE signal is the chip enable output to the external RF chip. When the RFCE signal is driven high,

the RF chip power is controlled by the settings of its power control registers. When the RFCE signal is

driven low, the RF chip is powered-down. However, the serial interface is still operational and the

CP3SP33 can still access the RF chip internal control registers.

The RFCE signal is the alternate function of the general-purpose I/O pin PG1. At reset, this pin is in TRI-

STATE mode. Software must enable the alternate function of the PG1 pin to give control over this signal

to the RF interface.

During Bluetooth power-down phases, the CP3SP33 provides a mechanism to reduce the power

consumption of an external RF chip by driving the RFCE signal of the RF interface to a logic low level.

This feature is available when the Power Management Module of the CP3SP33 has enabled the

Hardware Clock Control mechanism. (However, the current version of the radio chip does not implement a

power-reduction mode.)

19.1.1.5 SCLK

The SCLK signal is the serial interface shift clock output. The CP3SP33 always acts as the master of the

serial interface and therefore always provides the shift clock. The SCLK signal is the alternate function of

the general-purpose I/O pin PG3. At reset, this pin is in TRI-STATE mode. Software must enable the

alternate function of the PG3 pin to give control over this signal to the RF interface.

Bluetooth Controller

117

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