CP3SP33SMSSLASHNOPB datasheet(120/407 Pages) TI1

120 / 407 page

SLE

SCLK

SDAT

DS015

D10

D11

D12

SLE

SCLK

SDAT

DS014

D10

D11

D12

CP3SP33

SNOSCW5 – MAY 2013

www.ti.com

Read Operation

When the R/W bit is set, data is shifted out of the radio chip on the rising edge of SCLK. Data is sampled

by the CP3SP33 on the falling edge of SCLK. On reception of the read command (R/W = 1), the radio

chip takes control of the serial interface data line. The received 16-bit data is loaded by the CP3SP33 after

the first falling edge of SCLK when SLE is high. When SLE is high, the radio chip releases the SDAT line

again on the next rising edge of SCLK. The CP3SP33 takes control of the SDAT line again after the

following rising edge of SCLK. Which radio chip register is read, depends on the state of the four address

bits, Address[4:0]. The transfer is always 16 bits, without regard to the actual size of the register.

Unimplemented bits contain undefined data. Figure 19-5 shows the timing for the read operation .

Figure 19-5. Serial Interface 16-bit Fast-Write Timing

Figure 19-6. Serial Interface 8-bit Fast-Write Timing

32-Bit Write Operation

On the LMX5252, a 32-bit register is loaded by writing to the same register address twice. The first write

loads the high word (bits 31:16), and the second write loads the low word (bits 15:0). The two writes must

be separated by at least two clock cycles. For a 4-MHz clock, the minimum separation time is 500 ns.

The value read from a 32-bit register is a counter value, not the contents of the register. The counter value

indicates which words have been written. If the high word has been written, the counter reads as 0000h. If

both words have been written, the counter reads as 0001h. The value returned by reading a 32-bit register

is independent of the contents of the register.

Figure 19-7 and Figure 19-8 show the timing for 32-bit register writing and reading.

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CP3SP33SMS/NOPB Datasheet(PDF) 120 Page - Texas Instruments