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FS5502 Datasheet(PDF) 19 Page - NXP Semiconductors

Part # FS5502
Description  High voltage PMIC with multiple SMPS and LDO
PDF  113 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

FS5502 Datasheet(HTML) 19 Page - NXP Semiconductors

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NXP Semiconductors
FS5502
High voltage PMIC with multiple SMPS and LDO
Bit
Symbol
Description
LDO1 behavior in case of TSD
0
Regulator shutdown
1
Regulator shutdown and state machine transition to DEEP-FS
17
LDO1TSDCFG
Reset condition: POR
VPRE low-side slew rate control
00
130 mA typical drive capability - slow
01
260 mA typical drive capability - medium
10
520 mA typical drive capability - fast
11
900 mA typical drive capability - ultra fast
12 to 11
VPRESRLS[1:0]
Reset condition: POR
VPRE high-side slew rate control
00
130 mA typical drive capability - slow
01
260 mA typical drive capability - medium
10
520 mA typical drive capability - fast
11
900 mA typical drive capability - ultra fast
9 to 8
VPRESRHS[1:0]
Reset condition: POR
Table 14. M_REG_CTRL2 register bit description...continued
10.7 M_CLOCK register
Bit
23
22
21
20
19
18
17
16
Write
MOD_CONF
FOUT_MUX_SEL[3:0]
FOUT_PHASE[2:0]
Read
MOD_CONF
FOUT_MUX_SEL[3:0]
FOUT_PHASE[2:0]
Reset
0
0
0
0
0
0
0
0
Table 15. M_CLOCK register bit allocation
Bit
15
14
13
12
11
10
9
8
Write
FOUT_
CLK_SEL
EXT_
FIN_SEL
FIN_DIV
MOD_EN
CLK_TUNE[3 :0]
Read
FOUT_
CLK_SEL
RESERVED
FIN_DIV
MOD_EN
CLK_TUNE[3 :0]
Reset
0
0
0
0
0
0
0
0
Bit
Symbol
Description
Modulation configuration of main oscillator
0
range ± 5 % 23 kHz
1
range ± 5 % 94 kHz
23
MOD_CONF
Reset condition: POR
22 to 19
FOUT_MUX_SEL[3:0]
See Table 68
Table 16. M_CLOCK register bit description
FS5502
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 4 — 27 October 2021
19 / 113



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