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FS5502 Datasheet(PDF) 94 Page - NXP Semiconductors

Part # FS5502
Description  High voltage PMIC with multiple SMPS and LDO
PDF  113 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

FS5502 Datasheet(HTML) 94 Page - NXP Semiconductors

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NXP Semiconductors
FS5502
High voltage PMIC with multiple SMPS and LDO
TA = −40 °C to 125 °C, unless otherwise specified. VSUP = VSUP_UVH to 36 V, unless otherwise specified. All voltages referenced to
ground.
Symbol
Parameter
Min
Typ
Max
Unit
RSTBVIL
Low level input voltage threshold
1.0
—
—
V
RSTBVIH
High level input voltage threshold
—
—
2.0
V
RSTBHYST
Input voltage hysteresis
100
—
—
mV
RSTBVOL
Low level output voltage (I = 2.0 mA)
—
—
0.5
V
RSTBRPB
Internal pull-down resistor
200
400
800
kΩ
RSTBILIM
Current limitation
4.0
—
20
mA
RSTBTFB
Feedback filtering time
8.0
—
15
μs
RSTBTSC
Short to high filtering time
500
—
800
us
RSTBTLG
Long pulse (configurable with RSTB_DUR bit)
9.0
—
11
ms
RSTBTST
Short pulse (configurable with RSTB_DUR bit)
0.9
—
1.1
ms
RSTBT8S
8 second timer
7.0
8.0
9.0
s
RSTBTRELEASE
Time to release RSTB from Wake-up or POR with
all regulators started in Slot 0
—
8
—
ms
Table 91. RSTB electrical characteristics
28 Package information
FS5502 package is a QFN (sawn), thermally enhanced wettable flanks, 8 x 8 x 0.85 mm,
0.5 mm pitch, 56 pins. The assembly can be done at two different NXP assembly sites
with slight wettable flank difference but sharing the same PCB footprint.
FS5502
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 4 — 27 October 2021
94 / 113



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