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FS5502 Datasheet(PDF) 22 Page - NXP Semiconductors

Part # FS5502
Description  High voltage PMIC with multiple SMPS and LDO
PDF  113 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

FS5502 Datasheet(HTML) 22 Page - NXP Semiconductors

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NXP Semiconductors
FS5502
High voltage PMIC with multiple SMPS and LDO
10.9 M_INT_MASK2 register
Bit
23
22
21
20
19
18
17
16
Write
0
0
0
0
0
VBOSUVH_
M
COM_M
VPRE_
FB_OV_M
Read
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
VBOSUVH_
M
COM_M
VPRE_
FB_OV_M
Reset
0
0
0
0
0
0
0
0
Table 19. M_INT_MASK2 register bit allocation
Bit
15
14
13
12
11
10
9
8
Write
0
VSUPUV7_M
0
VPREUVH_
M
VSUPUVL_M VSUPUVH_
M
WAKE1_M
WAKE2_M
Read
RESERVED VSUPUV7_M RESERVED
VPREUVH_
M
VSUPUVL_M VSUPUVH_
M
WAKE1_M
WAKE2_M
Reset
0
0
0
0
0
0
0
0
Bit
Symbol
Description
Inhibit INTERRUPT for VBOS_UVH any transition
0
INT not masked
1
INT masked
18
VBOSUVH_M
Reset condition: POR
Inhibit INTERRUPT for COM any transition
0
INT not masked
1
INT masked
17
COM_M
Reset condition: POR
Inhibit INTERRUPT for VPRE_FB_OV
0
INT not masked
1
INT masked
16
VPRE_FB_OV_M
Reset condition: POR
Inhibit INTERRUPT for VSUP_UV7
0
INT not masked
1
INT masked
14
VSUPUV7_M
Reset condition: POR
Inhibit INTERRUPT for VSUP_UVH
0
INT not masked
1
INT masked
12
VREUVH_M
Reset condition: POR
Inhibit INTERRUPT for VSUP_UVL
0
INT not masked
1
INT masked
11
VSUPUVL_M
Reset condition: POR
Table 20. M_INT_MASK2 register bit description
FS5502
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 4 — 27 October 2021
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