FS5502 datasheet(77/113 Pages) NXP

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NXP Semiconductors

FS5502

High voltage PMIC with multiple SMPS and LDO

19.3 PSYNC for two FS5502

PSYNC function allows to manage complex start up sequence with multiple power

management ICs like two FS5502 (OTP_PSYNC_CFG = 0) or one FS5502 plus one

PF82 (OTP_PSYNC_CFG = 1). This function is enabled with the OTP_PSYNC_EN bit.

When PSYNC is used to synchronize two FS5502, PSYNC pin of each device shall

be connected together and pulled up to VBOS pin of the FS5502 master device as

shown in Figure 24. In this configuration, FS5502 #1 state machine stops before FS5502

#1_VPRE starts and waits for FS5502 #2 to synchronize FS5502#2_VPRE start.

aaa-033204

sync_in

to digital

FS5502 #1

PSYNC

sync_out

from digital

VBOS

PSYNCIPD

PSYNCRPU

PSYNCCOUT

sync_in

to digital

FS5502 #2

PSYNC

sync_out

from digital

VBOS

PSYNCIPD

Figure 24. Synchronization of two FS5502

aaa-033205

FS5502 #2 ready

FS5502 #1 ready

VSUP

FS5502 #1,

Sync_out

FS5502 #1,

VPRE

PSYNC

FS5502 #1,

Sync_in

FS5502 #2,

Sync_out

FS5502 #2,

VPRE

FS5502 #2,

Sync_in

FS5502 ready means VSUP > VSUP_UVH and WAKE1

or WAKE2 > WAKE12VIH

During T, FS5502 #1 Sync_in is held low by FS5502 #2

Sync_out

Whatever the start up delay T between the 2 x FS5502

devices, PSYNC synchronization allows both VPRE to

start at the same time.

Figure 25. Two FS5502 synchronization timing diagram

FS5502

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 27 October 2021

77 / 113

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