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FS5502 Datasheet(PDF) 32 Page - NXP Semiconductors

Part # FS5502
Description  High voltage PMIC with multiple SMPS and LDO
PDF  113 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

FS5502 Datasheet(HTML) 32 Page - NXP Semiconductors

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NXP Semiconductors
FS5502
High voltage PMIC with multiple SMPS and LDO
Bit
15
14
13
12
11
10
9
8
Write
RESERVED
RESERVED
RESERVED
RESERVED
VMON1_OV_
FS_IMPACT[1:0]
VMON1_UV_
FS_IMPACT[1:0]
Read
RESERVED
RESERVED
RESERVED
RESERVED
VMON1_OV_
FS_IMPACT[1:0]
VMON1_UV_
FS_IMPACT[1:0]
Reset
1
1
0
1
1
1
0
1
Bit
Symbol
Description
11 to 10
VMON1_OV_FS_IMPACT[1:0]
9 to 8
VMON1_UV_FS_IMPACT[1:0]
See Table 86
Table 42. FS_I_OVUV_SAFE_REACTION2 register bit description
11.6 FS_I_FSSM register
Bit
23
22
21
20
19
18
17
16
Write
FLT_ERR_CNT_LIMIT[1:0]
0
RESERVED
RESERVED
0
RSTB_DUR
0
Read
FLT_ERR_CNT_LIMIT[1:0]
RESERVED
RESERVED
RESERVED
RESERVED
RSTB_DUR
RESERVED
Reset
0
1
0
1
0
0
0
0
Table 43. FS_I_FSSM register bit allocation
Bit
15
14
13
12
11
10
9
8
Write
RESERVED
0
RESERVED
DIS_8s
0
0
0
0
Read
RESERVED
RESERVED
RESERVED
DIS_8s
FLT_ERR_CNT[3:0]
Reset
1
0
0
0
0
0
0
1
Bit
Symbol
Description
23 to 22
FLT_ERR_CNT_LIMIT[1:0]
See Table 89
RSTB pulse duration configuration
0
10 ms
1
1.0 ms
17
RSTB_DUR
Reset condition: POR
Disable 8 s timer
0
RSTB low 8 s counter enabled
1
RSTB low 8 s counter disabled
12
DIS_8s
Reset condition: POR
Table 44. FS_I_FSSM register bit description
FS5502
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 4 — 27 October 2021
32 / 113



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