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FS5502 Datasheet(PDF) 89 Page - NXP Semiconductors |
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FS5502 Datasheet(HTML) 89 Page - NXP Semiconductors |
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89 / 113 page  NXP Semiconductors FS5502 High voltage PMIC with multiple SMPS and LDO VDDIO_OV_FS_IMPACT[1:0] VDDIO OV impact on RSTB 00 No effect on RSTB 01 Reserved 1x (default) RSTB is asserted Reset condition POR Table 84. VDDIO error impact configuration VDDIO_UV_FS_IMPACT[1:0] VDDIO UV impact on RSTB 00 No effect on RSTB 01 (default) No effect on RSTB 1x RSTB is asserted Reset condition POR TA = −40 °C to 125 °C, unless otherwise specified. VSUP = VSUP_UVH to 36 V, unless otherwise specified. All voltages referenced to ground. Symbol Parameter Min Typ Max Unit VDDIO_OV_min Overvoltage threshold minimum — +4.5 — % VDDIO_OV_max Overvoltage threshold maximum — +12 — % VDDIO_OV_step Overvoltage threshold step (OTP_ VDDIOOVTH[7:0] bits) — +0.5 — % VDDIO_OV_acc Overvoltage threshold accuracy −2 — 2 % 20 25 30 μs TVDDIO_OV Overvoltage filtering time (OTP_VDDIO_OV_ DGLT bit) 40 45 50 μs VDDIO_UV_min Undervoltage threshold minimum — −4.5 — % VDDIO_UV_max Undervoltage threshold maximum — −12 — % VDDIO_UV_step Undervoltage threshold step (OTP_ VDDIOUVTH[7:0] bits) — −0.5 — % VDDIO_UV_acc Undervoltage threshold accuracy −2 — 2 % 2.5 5 7.5 μs 10 15 20 μs 20 25 30 μs TVDDIO_UV Undervoltage filtering time (OTP_VDDIO_UV_ DGLT[1:0] bits) 35 40 45 μs Table 85. VDDIO electrical characteristics 27.2.4 VMON1 monitoring Each VMON1 monitoring feature is enabled by OTP. VMON1 input pin can be connected to VPRE, LDO1, BUCK3 or even an external regulator. In order to turn OFF the regulator in case of Overvoltage detection, the configuration of which regulator is connected to VMON1 is done by I2C in the register M_VMON_REGx. If an external regulator (not delivered by the FS5502) is connected to VMON1, this regulator cannot be turned OFF, but the Overvoltage flag is reported to the MCU, which can take appropriate action. In all cases, the fail-safe reaction on RSTB is configured with VMON1_OV/ UV_FS_IMPACT[1:0] bits. FS5502 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 4 — 27 October 2021 89 / 113 |
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