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FS5502 Datasheet(PDF) 57 Page - NXP Semiconductors |
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FS5502 Datasheet(HTML) 57 Page - NXP Semiconductors |
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57 / 113 page  NXP Semiconductors FS5502 High voltage PMIC with multiple SMPS and LDO TA = −40 °C to 125 °C, unless otherwise specified. VSUP = VSUP_UVH to 36 V, unless otherwise specified. All voltages referenced to ground. Symbol Parameter Min Typ Max Unit Inductor for FPRE_SW = 455 kHz 4.7 6.8 10 μH LVPRE Inductor for FPRE_SW = 2.55 MHz 1.5 2.2 4.7 μH VPRE_LOAD_REG_455k Transient load regulation at 455 kHz VSUP = 6.0 V to 36 V (LVPRE = 6.8 μH, COUT_PRE = 66 μF, from 1.0 A to 3.0 A, di/dt = 300 mA/μs) −3 — 3 % VPRE_LOAD_REG_2.2M Transient load regulation at 2.22 MHz VSUP = 6.0 V to 18 V (LVPRE = 2.2 μH, COUT_PRE = 44 μF, from 1.0 A to 3.0 A, di/dt = 300 mA/μs) −3 — 3 % VPRE_LINE_REG_455k Transient line regulation at 455 kHz VSUP = 6.0 V to 18 V and VSUP = 12 V to 36 V (Cin = 47 µF + PI filter, LVPRE = 6.8 μH, COUT_PRE = 66 µF, dv/dt = 100 mV/µs) −3 — 3 % VPRE_LINE_REG_2.2M Transient line regulation at 2.2 MHz VSUP = 6.0 V to 18 V (Cin = 47 µF + PI filter, LVPRE = 6.8 μH, COUT_PRE = 44 µF, dv/dt = 100 mV/µs) −3 — 3 % VPRE_RIPPLE_455k Ripple at 455 kHz VSUP = 12 V and VSUP = 24 V (LVPRE = 6.8 µH, COUT_PRE = 66 µF, VPRE = 3.3 V and 5.0 V, IPRE = 4.0 A) 1 — 1 % VPRE_RIPPLE_2.2M Ripple at 2.22 MHz VSUP = 12 V (LVPRE = 2.2 µH, COUT_PRE = 44 µF, VPRE = 3.3 V and 5.0 V, IPRE = 2.0 A −0.5 — 0.5 % TPRE_ON_MIN HS minimum ON time 15 25 35 ns TPRE_OFF_MIN HS minimum OFF time 20 40 60 ns RSHUNT Current sense resistor (±1 %) 10 — 20 mΩ VPRE_LIM_GAIN Current sense amplifier gain 4.5 5 5.5 37 50 63 mV 60.8 80 99.2 mV 93.6 120 146.4 mV VPRE_LIM_TH1 Current sense amplifier peak detection threshold (OTP_VPREILIM[1:0] bits) 117 150 183 mV ILIM_PRE = VPRE_LIM_TH / RSHUNT Inductor peak current limitation range (RSHUNT = 10 mΩ, VPRE_LIM_TH1 = 50 mV) 3.75 5.0 6.25 A ILIM_PRE Inductor peak current limitation range (RSHUNT = 10 mΩ, VPRE_LIM_TH1 = 150 mV) To be recalculated for different RSHUNT and different VPRE_LIM_TH 12 15 18 A VPRE_DRV HS and LS gate driver output voltage — VBOS — V 60 130 220 mA 120 260 430 mA 220 520 860 mA IPRE_GATE_DRV HS and LS gate driver pull up and pull down current capability (OTP_VPRESRHS[1:0] and OTP_VPRESRLS[1:0] bits by default + VPRESRHS[1:0] and VPRESRLS[1:0] bits by I2C) 420 900 1490 mA Effective output capacitor for FPRE_SW = 455 kHz 44 66 220 μF Effective output capacitor for FPRE_SW = 2.22 MHz 22 44 110 µF COUT_PRE Output decoupling capacitor — 0.1 — μF Input capacitor (Cpi2) 20 — — μF CIN_PRE Input decoupling capacitor — 0.1 — μF IPRE_DRV Combined HS + LS gate driver average current capability IPRE_DRV < VPRE_SW × (QCHS + QCLS) with QCHS = gate charge of Q2 at VBOS with QCLS = gate charge of Q1 at VBOS — — 30 mA gmEA Error amplifier transconductance 1.0 1.5 2.1 mS Table 62. VPRE electrical characteristics...continued FS5502 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 4 — 27 October 2021 57 / 113 |
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