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FS5502 Datasheet(PDF) 70 Page - NXP Semiconductors

Part # FS5502
Description  High voltage PMIC with multiple SMPS and LDO
PDF  113 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

FS5502 Datasheet(HTML) 70 Page - NXP Semiconductors

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NXP Semiconductors
FS5502
High voltage PMIC with multiple SMPS and LDO
Ibuck3 (A)
0
2.75
0.25
2.5
1.25
0.75
2.25
1.75
1
2
0.5
1.5
Buck3 Efficiency vs Ibuck3
aaa-031005
100
65
1.2 V
2.3 V
3.3 V
Cin
Ext. C and L
Int. MOSFETs
60
µF
ESR Cin
10
mΩ
Cout
44
µF
ESR Cout
10
mΩ
L coil
1
µH
DCR coil
20
mΩ
HS_Rdson
135
mΩ
QHS
0.5
nC
THS_sw
3
ns
GHS_drive
5
V
LS_Rdson
80
mΩ
QLS
0.5
nC
TLS_sw
3
ns
GLS_drive
5
V
BUCK3 Efficiency
70
75
80
85
90
95
Figure 21. BUCK3 theoretical efficiency
17 Linear voltage regulator: LDO1
17.1 Functional description
An LDO1 block is a linear voltage regulator. The output voltage is configurable by OTP
from 1.1 V to 5.0 V. A minimum voltage drop is required depending on the output current
capability (0.5 V for 150 mA and 1.0 V for 400 mA). The LDO current capability is linear
with the voltage drop and can be estimated to I(mA) = 500 x VLDO1_DROP – 100 for
intermediate voltage drop between 0.5 V and 1.0 V.
LDO1 input supply is externally connected to VPRE or another supply. An overcurrent
detection and a thermal shutdown are implemented on LDO1 to protect the internal pass
device.
17.2 Application schematics
aaa-032950
I2C
INTERFACE
VLDO1_EN
LDO1_IN
VLDO1
CIN_LDO1
COUT_LDO1
VLDO1_IN
discharge
VREF
VLDO1
Figure 22. LDO1 block diagram
FS5502
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 4 — 27 October 2021
70 / 113



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