XM014429B datasheet(11/83 Pages) XMOS

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XU6--QF6B Datasheet

Product Overview

Logical cores

Each tile has 8 active logical cores, which issue instructions down a shared ve-stage

pipeline. Instructions from the active cores are issued round-robin. If up to ve logical

cores are active, each core is allocated a fth of the processing cycles. If more than ve

logical cores are active, each core is allocated at least /n cycles (for n cores). Figure

shows the guaranteed core performance depending on the number of cores used.

Speed

active logical cores:

grade

MIPS

Frequency

Minimum issue rate per logical core (MHz)

MIPS

MHz

Figure :

Logical core

performance

When executing code from internal memory, there is no way that the performance of a

logical core can be reduced below these predicted levels (unless priority threads are used:

in this case the guaranteed minimum performance is computed based on the number of

priority threads as dened in the architecture manual). Because cores may be delayed

on I/O, however, their unused processing cycles can be taken by other cores. This means

that for more than ve logical cores, the performance of each core is often higher than

the predicted minimum but cannot be guaranteed.

The logical cores are triggered by events instead of interrupts and run to completion. A

logical core can be paused to wait for an event.

xTIME scheduler

The xTIME scheduler handles the events generated by xCORE Tile resources, such as

channel ends, timers and I/O pins. It ensures that all events are serviced and synchro-

nized, without the need for an RTOS. Events that occur at the I/O pins are handled by the

Hardware-Response ports and fed directly to the appropriate xCORE Tile. An xCORE Tile

can also choose to wait for a specied time to elapse, or for data to become available on

a channel.

Tasks do not need to be prioritised as each of them runs on their own logical xCORE. It

is possible to share a set of low priority tasks on a single core using cooperative multi-

tasking.

Hardware Response Ports

Hardware Response ports connect an xCORE tile to one or more physical pins and as

such dene the interface between hardware attached to the XU6--QF6B, and the

software running on it. A combination of bit, bit, 8bit, 6bit and bit ports are available.

All pins of a port provide either output or input. Signals in different directions cannot be

mapped onto the same port.

The port logic can drive its pins high or low, or it can sample the value on its pins, option-

ally waiting for a particular condition. Ports are accessed using dedicated instructions

that are executed in a single processor cycle. xcore.ai IO pins can be used as open drain

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