XM014429B datasheet(49/83 Pages) XMOS

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XU6--QF6B Datasheet

Data watchpoint address

DBG_DWATCH_ADDR1 0x50 .. 0x53

This set of registers contains the rst address for the four data watchpoints. Condition

of a watchpoint is met if the effective address of an instruction is greater than or equal

to the value in this register.

The CTRL register for the watchpoint will dictate whether the watchpoint triggers on

stores only or on loads and stores, and whether it requires either condition A or B, or

both A and B.

Bits

Perm

Init

Description

Identier

DRW

Value.

ALL_BITS

.. x:

Data

watchpoint

address

Data watchpoint address

DBG_DWATCH_ADDR2 0x60 .. 0x63

This set of registers contains the second address for the four data watchpoints. Con-

dition B of a watchpoint is met if the effective address of an instruction is less than or

equal to the value in this register.

The CTRL register for the watchpoint will dictate whether the watchpoint triggers on

stores only or on loads and stores, and whether it requires either condition A or B, or

both A and B.

Bits

Perm

Init

Description

Identier

DRW

Value.

ALL_BITS

x6 .. x6:

Data

watchpoint

address

Data breakpoint control register

DBG_DWATCH_CTRL 0x70 .. 0x73

This set of registers controls each of the four data watchpoints.

Bits

Perm

Init

Description

Identier

Reserved

DRW

A bit for each thread in the machine allowing the breakpoint to be en-

abled individually for each thread.

BRK_THREADS

Reserved

DRW

When the breakpoints will be be triggered on loads.

BRK_LOAD

DRW

Determines the break condition: = A AND B, = A OR B. DBRK_CONDITION

DRW

When the breakpoint is enabled.

BRK_ENABLE

.. x:

Data

breakpoint

control

XM014429B Datasheet(PDF) 49 Page - Xmos Ltd.

XM014429B Datasheet(HTML) 49 Page - Xmos Ltd.

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