XM014429B datasheet(47/83 Pages) XMOS

47 / 83 page

XU6--QF6B Datasheet

B.6 DGETREG operand

DBG_T_REG 0x14

Bits

Perm

Init

Description

Identier

Reserved

DRW

DBG_T_REG_REG

DGETREG

operand

Debug interrupt type

DBG_TYPE 0x15

Bits

Perm

Init

Description

Identier

Reserved

DRW

Number of the hardware breakpoint/watchpoint which caused the

interrupt (always

for =HOST= and =DCALL=). If multiple break-

points/watchpoints trigger at once, the lowest number is taken.

DBG_TYPE_HW_NUM

DRW

Number of thread which caused the debug interrupt (always in the

case of =HOST=).

DBG_TYPE_T_NUM

Reserved

DRW

Indicates the cause of the debug interrupt

: Host initiated a debug interrupt through JTAG

: Program executed a DCALL instruction

: Instruction breakpoint

: Data watch point

: Resource watch point

DBG_TYPE_CAUSE

Debug

interrupt type

B.8 Debug interrupt data

DBG_DATA 0x16

On a data watchpoint, this register contains the effective address of the memory oper-

ation that triggered the debugger. On a resource watchpoint, it countains the resource

identier.

Bits

Perm

Init

Description

Identier

DRW

Value.

ALL_BITS

x6:

Debug

interrupt data

Debug core control

DBG_RUN_CTRL 0x18

This register enables the debugger to temporarily disable logical cores. When returning

from the debug interrupts, the cores set in this register will not execute. This enables

single stepping to be implemented.

XM014429B Datasheet(PDF) 47 Page - Xmos Ltd.

XM014429B Datasheet(HTML) 47 Page - Xmos Ltd.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83

Datasheet Download

Link URL