XM014429B datasheet(64/83 Pages) XMOS

64 / 83 page

XU6--QF6B Datasheet

Bits

Perm

Init

Description

Identier

If set to , the secondary PLL is used as a source for the application

clock divider. By default, the output of the core PLL is used.

SS_APP_CLK_FROM_APP_PLL

Reserved

Application clock divider disable. When set to , the divider is enabled,

and pin XD will be connected to the application clock rather than to

port D.

SS_APP_CLK_DIV_DISABLE

Application clock divider. When set to X, the output of the secondary

PLL will be divided by 2(X +1) in order to form the output on the output

SS_APP_CLK_DIV

xE:

Application

clock divider

Secondary PLL settings

SS_APP_PLL_CTL 0x0F

A secondary on-chip PLL multiplies the input clock up to a higher frequency clock. See

Section . .

Bits

Perm

Init

Description

Identier

Reserved

If set to , set the APP PLL to be bypassed

SS_APP_PLL_BYPASS

If set to , use the output of the core PLL as input, otherwise use the

crystal oscillator as input.

SS_APP_PLL_INPUT_FROM_SYS_PLL

If set to , enable the secondary PLL

SS_APP_PLL_ENABLE

Reserved

Output divider value range from to . OD value.

SS_PLL_CTL_POST_DIVISOR

Reserved

Feedback multiplication ratio, range from (x) to 8

(xFFF).

F value.

SS_PLL_CTL_FEEDBACK_MUL

Reserved

Oscilator input divider value range from (x) to 6 (xF). R value.

SS_PLL_CTL_INPUT_DIVISOR

xF:

Secondary

PLL settings

Reserved

XCORE0_GLOBAL_DEBUG_CONFIG 0x10

Reserved.

Bits

Perm

Init

Description

Identier

Reserved

Reserved.

GLOBAL_DEBUG_ENABLE_GLOBAL_DEBUG_REQ

Reserved.

GLOBAL_DEBUG_ENABLE_INDEBUG

Reserved

XM014429B Datasheet(PDF) 64 Page - Xmos Ltd.

XM014429B Datasheet(HTML) 64 Page - Xmos Ltd.

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