XM014429B datasheet(27/83 Pages) XMOS

27 / 83 page

XU6--QF6B Datasheet

Board Integration

The device has power and ground pins for different supplies. Several pins of each type

may be provided to minimize the effect of inductance within the package, all of which

must be connected.

VDD pins for the xCORE Tile. The VDD supply should be well decoupled at high frequen-

cies. Place many (at least eight)

nF low inductance multi-layer ceramic capacitors

close to the chip between the supplies and GND.

VDDIO pins for the I/O lines. Separate I/O supplies are provided for the left, bottom, top,

and right side of the package; different I/O voltages may be supplied on those. The sig-

nal description (Section ) species which I/O is powered from which power-supply.

The VDDIO supplies should be decoupled close to the chip by several

nF low in-

ductance multi-layer ceramic capacitors between the supplies and GND, for example,

one

low inductance MLCCs on each supply pin.

PLL_AVDD pin for the PLL. The PLL_AVDD supply should be separated from the other

noisier supplies on the board. The PLL requires a very clean power supply, and a low

pass lter (for example, a µF multi-layer ceramic capacitor and a ferrite of 6

ohm

MHz and DCR < ohm, eg, Taiyo Yuden BKHLM6-T) is recommended

on this pin.

A USB_VDD8 pin for the analogue .8V supply to the USB-PHY. You can leave USB_VDD8

unconnected if USB is not used in the design.

A USB_VDD pin for the analogue .V supply to the USB-PHY. You can leave USB_VDD

unconnected if USB is not used in the design.

GND for all other supplies, including VDD and VDDIO.

All ground pins must be connected directly to the board ground. The ground side of the

decoupling capacitors should have as short a path back to the GND pins as possible. A

bulk decoupling capacitor of at least

uF should be placed on VDD and VDDIO supplies.

The power supplies must be brought up monotonically and input voltages must not ex-

ceed specication at any time.

Power sequencing is summarised in Figure

. VDDIO and VDD can ramp up indepen-

dently. In order to reduce stresses on the device, it is preferable to make them ramp up

within a short time of each other, no more than

ms apart. You must ensure that the

VDDIOL, VDDIOT, and VDDIOR domains are valid before the device is taken out of reset,

as the boot pins are on VDDIOL. If you use a single .8V VDDIO power supply, then the

on-chip power-on-reset will ensure that reset stays low until all supplies are valid. If you

use multiple power supplies, then you must either ensure that RST_N stays asserted until

the VDDIOL/R/T domains are valid, or ensure that VDDIOL/R/T are valid by the time that

VDDIOB8 and VDD are valid.

Differential pair signal routing and placement

If you are using the USB PHY , then you should route the differential pair marked D+ and

D- carefully in order to ensure signal integrity. The D+ and D- lines are the positive and

negative data polarities of a high speed signal respectively. Their high-speed differential

XM014429B Datasheet(PDF) 27 Page - Xmos Ltd.

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