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XM014429B Datasheet(PDF) 48 Page - Xmos Ltd.

Part # XM014429B
Description  XCore xcore.ai Microcontroller IC 32-Bit 16-Core 2400MIPs 8KB (8K x 8) OTP 60-QFN (7x7)
PDF  83 Pages
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Manufacturer  XMOS [Xmos Ltd.]
Direct Link  https://www.xmos.ai/
Logo XMOS - Xmos Ltd.

XM014429B Datasheet(HTML) 48 Page - Xmos Ltd.

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XU6--QF6B Datasheet
Bits
Perm
Init
Description
Identier
:8
RO
-
Reserved
:
DRW
-hot vector dening which threads are stopped when not in debug
mode. Every bit which is set prevents the respective thread from
running.
DBG_RUN_CTRL_STOP
x8:
Debug core
control
B.
Debug scratch
DBG_SCRATCH 0x20 .. 0x27
A set of registers used by the debug ROM to communicate with an external debugger,
for example over JTAG. This is the same set of registers as the Debug Scratch registers
in the xCORE tile conguration.
Bits
Perm
Init
Description
Identier
:
DRW
Value.
ALL_BITS
x
.. x:
Debug scratch
B.
Instruction breakpoint address
DBG_IBREAK_ADDR 0x30 .. 0x33
This register contains the address of the instruction breakpoint. If the PC matches this
address, then a debug interrupt will be taken. There are four instruction breakpoints that
are controlled individually.
Bits
Perm
Init
Description
Identier
:
DRW
Value.
ALL_BITS
x
.. x:
Instruction
breakpoint
address
B.
Instruction breakpoint control
DBG_IBREAK_CTRL 0x40 .. 0x43
This register controls which logical cores may take an instruction breakpoint, and under
which condition.
Bits
Perm
Init
Description
Identier
:
RO
-
Reserved
:6
DRW
A bit for each thread in the machine allowing the breakpoint to be en-
abled individually for each thread.
BRK_THREADS
:
RO
-
Reserved
DRW
When break when PC == IBREAK_ADDR. When = break when PC !=
IBREAK_ADDR.
IBRK_CONDITION
DRW
When the breakpoint is enabled.
BRK_ENABLE
x
.. x:
Instruction
breakpoint
control



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