XM014429B datasheet(17/83 Pages) XMOS

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XU6--QF6B Datasheet

Name

Frequency

Load

max ESR

Power

Cl1

, Cl2

Seiko Epson FA-8

.MDX-W

MHz

6 R

68 R

Multicomp MCSJK-U-.---6-B-

MHz

6 R

68 R

IQD LFXTAL8

MHz

68 R

TKC M-.MAAE-T

MHz

68 R

Figure

Example

crystals

Low power use

For systems that need to run in a low-power mode, the following sequence of operations

can be taken:

set the core clock divider to an appropriately high value. This will reduce performance

and power

set the PLL to a low frequency. This will reduce power consumption.

provide a clock into the XIN pin instead of using the oscillator circuit.

The power consumption of the PLL and oscillator circuits are listed in Section .6.

Reset logic

The device has an on-chip Power-on-Reset (POR). This keeps the chip in reset whilst the

supplies are coming up, as shown in Figure . The device assumes that the supplies

come up monotonically to reach their minimum operating voltages within the times spec-

ied in Section . . The POR resets the whole device to a dened state, including the

PLL conguration, the JTAG logic, the PHYs, and the cores. When in reset, all GPIO pins

have a pull-down enabled.

Voltage

comp.

VDD

VDDIOB18

PORST_N

RST_N

internal device reset_n

Internal

pull-up

Watchdog

internal jtag reset_n

Delay

Th(VDD)

Th(VDDIOB18)

T(POR)

Figure

Simplied

reset circuit

When the device comes out of reset, the boot procedure starts (Section ). The chip can

be reset externally using the RST_N pin. If required, the JTAG state machine can be reset

to its idle state by clocking TCK ve times whilst TMS is high.

If the chip needs to be reset at a later stage, this can be done from software using the

PLL control register (Appendix D. ). This soft resets everything except for the PLL logic.

It is therefore possible to reset keeping the current PLL settings.

XM014429B Datasheet(PDF) 17 Page - Xmos Ltd.

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