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XM014429B Datasheet(PDF) 52 Page - Xmos Ltd. |
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XM014429B Datasheet(HTML) 52 Page - Xmos Ltd. |
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52 / 83 page ![]() XU6--QF6B Datasheet C Tile Conguration The xCORE Tile control registers can be accessed using conguration reads and writes (use write_tile_config_reg(tileref, ...) and read_tile_config_reg(tileref, ...) for reads and writes). The identiers for the registers needs a prex “XS1_PSWITCH_” and a postx “_NUM”, and are declared in “xs1.h” Number Perm Description Register identier x CRO Device identication DEVICE_ID0 x CRO xCORE Tile description DEVICE_ID1 x CRO xCORE Tile description DEVICE_ID2 x CRW PSwitch permissions DBG_CTRL x CRW Cause debug interrupts DBG_INT x6 CRW xCORE Tile clock divider PLL_CLK_DIVIDER x CRO Security conguration SECU_CONFIG x .. x CRW Debug scratch DBG_SCRATCH x CRO PC of logical core T0_PC x CRO PC of logical core T1_PC x CRO PC of logical core T2_PC x CRO PC of logical core T3_PC x CRO PC of logical core T4_PC x CRO PC of logical core T5_PC x6 CRO PC of logical core 6 T6_PC x CRO PC of logical core T7_PC x6 CRO SR of logical core T0_SR x6 CRO SR of logical core T1_SR x6 CRO SR of logical core T2_SR x6 CRO SR of logical core T3_SR x6 CRO SR of logical core T4_SR x6 CRO SR of logical core T5_SR x66 CRO SR of logical core 6 T6_SR x6 CRO SR of logical core T7_SR Figure : Summary C. Device identication DEVICE_ID0 0x00 This register identies the xCORE Tile |
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