STC12LE5616AD datasheet(114/377 Pages) STC

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NOP

Function:

No Operation

Description:

Execution continues at the following instruction. Other than the PC, no registers or flags are

affected.

Example:

It is desired to produce a low-going output pulse on bit 7 of Port 2 lasting exactly 5 cycles. A

simple SETB/CLR sequence would generate a one-cycle pulse, so four additional cycles

must be inserted. This may be done (assuming no interrupts are enabled) with the instruction

sequence.

CLR

P2.7

NOP

SETB

P2.7

Bytes:

Cycles:

Encoding:

0 0 0

0 0 0 0

Operation:

NOP

(PC) ← (PC)+1

(PC)+1

ORL <dest-byte> , <src-byte>

Function:

Logical-OR for byte variables

Description:

ORL performs the bitwise logical-OR operation between the indicated variables, storing the

results in the destination byte. No flags are affected.

The two operands allow six addressing mode combinations. When the destination is the

Accumulator, the source can use register, direct, register-indirect, or immediate addressing;

when the destination is a direct address, the source can be the Accumulator or immediate

data.

Note: When this instruction is used to modify an output port, the value used as the original

port data will be read from the output data latch, not the input pins.

Example:

If the Accumulator holds 0C3H (11000011B) and R0 holds 55H (01010101B) then the

instruction,

ORL

A, R0

will leave the Accumulator holding the value 0D7H (11010111B).

When the destination is a directly addressed byte, the instruction can set combinations of bits

in any RAM location or hardware register. The pattern of bits to be set is determined by a

mask byte, which may be either a constant data value in the instruction or a variable

computed in the Accumulator at run-time.The instruction,

ORL

P1, #00110010B

will set bits 5,4, and 1of output Port 1.

114

STC12LE5616AD Datasheet(PDF) 114 Page - STCmicro Technology Co,.Ltd

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