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S75WS256NDFBAWMB Datasheet(PDF) 149 Page - SPANSION

Part # S75WS256NDFBAWMB
Description  Stacked Multi-Chip Product (MCP)
PDF  216 Pages
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Manufacturer  SPANSION [SPANSION]
Direct Link  http://www.spansion.com
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S75WS256NDFBAWMB Datasheet(HTML) 149 Page - SPANSION

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February 17, 2005 S75WS-N-00_A0
S75WS256Nxx Based MCPs
147
Advance
Information
Notes:
1. CLK may be High or Low, but must be static during asynchronous Read, synchronous Write, burst suspend, and DPD modes; and to achieve
standby power during standby and active modes.
2. The Wait polarity is configured through the bus configuration register (BCR[10]).
3. When LB# and UB# are in select mode (Low), DQ[15:0] are affected. When only LB# is in select mode, DQ[7:0] are affected. When only
UB# is in the select mode, DQ[15:8] are affected.
4. The device will consume active power in this mode whenever addresses are changed.
5. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external influence.
6. VIN = VCCQ or 0V; all device balls must be static (unswitched) to achieve standby current.
7. DPD is maintained until RCR is reconfigured.
8. Burst mode operation is initialized through the bus configuration register (BCR[15]).
Table 27.3 Bus Operations—Burst Mode
Mode
Power
CLK
(Note 1) ADV#
CE#
OE#
WE#
CRE
LB#/
UB#
Wait
(Note 2)
DQ[15:0]
(Note 3)Notes
Async Read
Active
X
L
L
L
H
L
L
Low-Z
Data-Out
4
Async Write
Active
X
LL
X
LLL
Low-Z
Data-In
4
Standby
Standby
X
X
H
X
X
L
X
High-Z
High-Z
5, 6
No Operation
Idle
X
X
L
X
X
L
X
Low-Z
X
4, 6
Initial Burst Read
Active
L
L
X
H
L
L
Low-Z
Data-Out
4, 8
Initial Burst Write
Active
L
L
H
L
L
X
Low-Z
Data-In
4, 8
Burst Continue
Active
H
L
X
X
L
X
Low-Z
Data-In or
Data-Out
4, 8
Burst Suspend
Active
X
X
L
H
X
L
X
Low-Z
High-Z
4, 8
Configuration
Register
Active
L
L
H
L
H
X
Low-Z
High-Z
8
DPD
Deep
Power-Down
X
X
H
X
X
X
X
High-Z
High-Z
7



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