PI7C8150AND datasheet(33/111 Pages) PERICOM

33 / 111 page

PI7C8150A

2-PORT PCI-TO-PCI BRIDGE

Page 33 of 111

APRIL 2006 – Revision 1.1

PI7C8150A can assert up to 9 unique address lines to be used as IDSEL signals for up to 9

devices on the secondary bus, for device numbers ranging from 0 through 8. Because of

electrical loading constraints of the PCI bus, more than 9 IDSEL signals should not be

necessary. However, if device numbers greater than 9 are desired, some external method of

generating IDSEL lines must be used, and no upper address bits are then asserted. The

configuration transaction is still translated and passed from the primary bus to the

secondary bus. If no IDSEL pin is asserted to a secondary device, the transaction ends in a

master abort.

PI7C8150A forwards Type 1 to Type 0 configuration read or write transactions as delayed

transactions. Type 1 to Type 0 configuration read or write transactions are limited to a

single 32-bit data transfer.

3.7.3

TYPE 1 TO TYPE 1 FORWARDING

Type 1 to Type 1 transaction forwarding provides a hierarchical configuration mechanism

when two or more levels of PCI-to-PCI bridges are used.

When PI7C8150A detects a Type 1 configuration transaction intended for a PCI bus

downstream from the secondary bus, PI7C8150A forwards the transaction unchanged to

the secondary bus. Ultimately, this transaction is translated to a Type 0 configuration

command or to a special cycle transaction by a downstream PCI-to-PCI bridge.

Downstream Type 1 to Type 1 forwarding occurs when the following conditions are met

during the address phase:

The lowest two address bits are equal to 01b.

The bus number falls in the range defined by the lower limit (exclusive)

in the secondary bus number register and the upper limit (inclusive) in

the subordinate bus number register.

The bus command is a configuration read or write transaction.

PI7C8150A also supports Type 1 to Type 1 forwarding of configuration write transactions

upstream to support upstream special cycle generation. A Type 1 configuration command

is forwarded upstream when the following conditions are met:

The lowest two address bits are equal to 01b.

The bus number falls outside the range defined by the lower limit (inclusive)

in the secondary bus number register and the upper limit (inclusive) in the subordinate

bus number register.

The device number in address bits AD[15:11] is equal to 11111b.

The function number in address bits AD[10:8] is equal to 111b.

The bus command is a configuration write transaction.

06-0057

PI7C8150AND Datasheet(PDF) 33 Page - Pericom Semiconductor Corporation