PI7C8150AND datasheet(88/111 Pages) PERICOM

88 / 111 page

PI7C8150A

2-PORT PCI-TO-PCI BRIDGE

Page 88 of 111

APRIL 2006 – Revision 1.1

Bit

Function

Type

Description

10:9

Test Mode For

All Counters at P

and S1

R/O

Controls the testability of the bridge’s internal counters.

The bits are used for chip test only.

00: all bits are exercised

01: byte 1 is exercised

10: byte 2 is exercised

11: byte 3 is exercised

Reset to 0

15:11

Reserved

R/O

Reserved. Returns 0 when read. Reset to 0.

14.1.30

ARBITER CONTROL REGISTER – OFFSET 40h

Bit

Function

Type

Description

24:16

Arbiter Control

R/W

Each bit controls whether a secondary bus master is assigned to the

high priority group or the low priority group.

Bits [24:16] correspond to request inputs S_REQ_L[8:0]

respectively.

Bit 24 corresponds to S_REQ_L[8]

Bit 16 corresponds to S_REQ_L[0]

0: low priority

1: high priority

Reset to 0

Priority of

Secondary

Interface

R/W

Controls whether the secondary interface of the bridge is in the high

priority group or the low priority group.

0: low priority

1: high priority

Reset to 1

31:26

Reserved

R/O

Reserved. Returns 0 when read. Reset to 0.

14.1.31

EXTENDED CHIP CONTROL REGISTER – OFFSET 48h

Bit

Function

Type

Description

Memory Read

Flow Through

Enable

R/W

Controls ability to do memory read flow through

0: Disable flow through during a memory read transaction

1: Enable flow through during a memory read transaction

Reset to 0

Park

R/W

Controls bus arbiter’s park function

0: Park to last master

1: Park to bridge

Reset to 0

15:2

Reserved

R/O

Reserved. Returns 0 when read. Reset to 0

06-0057

PI7C8150AND Datasheet(PDF) 88 Page - Pericom Semiconductor Corporation

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