PI7C8150AND datasheet(24/111 Pages) PERICOM

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PI7C8150A

2-PORT PCI-TO-PCI BRIDGE

Page 24 of 111

APRIL 2006 – Revision 1.1

The PI7C8150A can accept one DWORD of write data every PCI clock cycle.

That is, no target wait state is inserted. The write data is stored in an internal

posted write buffers and is subsequently delivered to the target.

The PI7C8150A continues to accept write data until one of the following events occurs:

The initiator terminates the transaction by de-asserting FRAME# and IRDY#.

An internal write address boundary is reached, such as a cache line boundary or an

aligned 4KB boundary, depending on the transaction type.

The posted write data buffer fills up.

When one of the last two events occurs, the PI7C8150A returns a target disconnect to the

requesting initiator on this data phase to terminate the transaction.

Once the posted write data moves to the head of the posted data queue, PI7C8150A asserts

its request on the target bus. This can occur while PI7C8150A is still receiving data on the

initiator bus. When the grant for the target bus is received and the target bus is detected in

the idle condition, PI7C8150A asserts FRAME_L and drives the stored write address out

on the target bus. On the following cycle, PI7C8150A drives the first DWORD of write

data and continues to transfer write data until all write data corresponding to that

transaction is delivered, or until a target termination is received. As long as write data

exists in the queue, PI7C8150A can drive one DWORD of write data each PCI clock cycle;

that is, no master wait states are inserted. If write data is flowing through PI7C8150A and

the initiator stalls, PI7C8150A will signal the last data phase for the current transaction at

the target bus if the queue empties. PI7C8150A will restart the follow-on transactions if the

queue has new data.

PI7C8150A ends the transaction on the target bus when one of the following conditions is

met:

All posted write data has been delivered to the target.

The target returns a target disconnect or target retry (PI7C8150A starts another

transaction to deliver the rest of the write data).

The target returns a target abort (PI7C8150A discards remaining write data).

The master latency timer expires, and PI7C8150A no longer has the target bus grant

(PI7C8150A starts another transaction to deliver remaining write data).

Section 3.8.3.2 provides detailed information about how PI7C8150A responds to target

termination during posted write transactions.

3.5.2

MEMORY WRITE AND INVALIDATE

Posted write forwarding is used for Memory Write and Invalidate transactions.

If offset 74h bits [8:7] = 11, the PI7C8150A disconnects Memory Write and Invalidate

commands at aligned cache line boundaries. The cache line size value in the cache line size

06-0057

PI7C8150AND Datasheet(PDF) 24 Page - Pericom Semiconductor Corporation

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