PI7C8150AND datasheet(38/111 Pages) PERICOM

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PI7C8150A

2-PORT PCI-TO-PCI BRIDGE

Page 38 of 111

APRIL 2006 – Revision 1.1

Table 3-8. Response to Posted Write Target Termination

Target Termination

Repsonse

Normal

No additional action.

Target Retry

Repeating write transaction to target.

Target Disconnect

Initiate write transaction for delivering remaining posted write data.

Target Abort

Set received-target-abort bit in the target interface status register. Assert

P_SERR# if enabled, and set the signaled-system-error bit in primary status

Note that when a target retry or target disconnect is returned and posted write data

associated with that transaction remains in the write buffers, PI7C8150A initiates another

write transaction to attempt to deliver the rest of the write data. If there is a target retry, the

exact same address will be driven as for the initial write trans-action attempt. If a target

disconnect is received, the address that is driven on a subsequent write transaction attempt

will be updated to reflect the address of the current DWORD. If the initial write transaction

is Memory-Write-and-Invalidate transaction, and a partial delivery of write data to the

target is performed before a target disconnect is received, PI7C8150A will use the memory

write command to deliver the rest of the write data. It is because an incomplete cache line

will be transferred in the subsequent write transaction attempt.

After the PI7C8150A makes 2

24 (default) write transaction attempts and fails to deliver all

posted write data associated with that transaction, PI7C8150A asserts P_SERR_L if the

primary SERR_L enable bit is set (bit 8 of command register for secondary bus) and

posted-write-non-delivery bit is not set. The posted-write-non-delivery bit is the bit 2 of

P_SERR_L event disable register (offset 64h). PI7C8150A will report system error. See

Section 6.4 for a discussion of system error conditions.

3.8.3.3

DELAYED READ TARGET TERMINATION RESPONSE

When PI7C8150A initiates a delayed read transaction, the abnormal target responses can

be passed back to the initiator. Other target responses depend on how much data the

initiator requests. Table 3-9 shows the response to each type of target termination that

occurs during a delayed read transaction.

PI7C8150A repeats a delayed read transaction until one of the following conditions is met:

PI7C8150A completes at least one data transfer.

PI7C8150A receives a master abort.

PI7C8150A receives a target abort.

PI7C8150A makes 2

24 (default) read attempts resulting in a response of target retry.

Table 3-9. Response to Delayed Read Target Termination

Target Termination

Response

Normal

If prefetchable, target disconnect only if initiator requests more data than read

from target. If non-prefetchable, target disconnect on first data phase.

Target Retry

Re-initiate read transaction to target

Target Disconnect

If initiator requests more data than read from target, return target disconnect to

initiator.

06-0057

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