PI7C8150AND datasheet(22/111 Pages) PERICOM

22 / 111 page

PI7C8150A

2-PORT PCI-TO-PCI BRIDGE

Page 22 of 111

APRIL 2006 – Revision 1.1

3.1

TYPES OF TRANSACTIONS

This section provides a summary of PCI transactions performed by PI7C8150A.

Table 3-1 lists the command code and name of each PCI transaction. The Master and

Target columns indicate support for each transaction when PI7C8150A initiates

transactions as a master, on the primary (P) and secondary (S) buses, and when PI7C8150A

responds to transactions as a target, on the primary (P) and secondary (S) buses.

Table 3-1. PCI Transactions

Types of Transactions

Initiates as Master

Responds as Target

Primary

Secondary

Primary

Secondary

0000

Interrupt Acknowledge

0001

Special Cycle

0010

I/O Read

0011

I/O Write

0100

Reserved

0101

Reserved

0110

Memory Read

0111

Memory Write

1000

Reserved

1001

Reserved

1010

Configuration Read

1011

Configuration Write

Y (Type 1 only)

1100

Memory Read Multiple

1101

Dual Address Cycle

1110

Memory Read Line

1111

Memory Write and Invalidate

As indicated in Table 3-1, the following PCI commands are not supported by

PI7C8150A:

PI7C8150A never initiates a PCI transaction with a reserved command code and, as

a target, PI7C8150A ignores reserved command codes.

PI7C8150A does not generate interrupt acknowledge transactions. PI7C8150A

ignores interrupt acknowledge transactions as a target.

PI7C8150A does not respond to special cycle transactions. PI7C8150A cannot

guarantee delivery of a special cycle transaction to downstream buses because of the

broadcast nature of the special cycle command and the inability to control the

transaction as a target. To generate special cycle transactions on other PCI buses,

either upstream or downstream, Type 1 configuration write must be used.

PI7C8150A neither generates Type 0 configuration transactions on the primary PCI

bus nor responds to Type 0 configuration transactions on the secondary PCI buses.

3.2

SINGLE ADDRESS PHASE

A 32-bit address uses a single address phase. This address is driven on P_AD[31:0], and

the bus command is driven on P_CBE[3:0]. PI7C8150A supports the linear increment

address mode only, which is indicated when the lowest two address bits are equal to zero.

06-0057

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