PI7C8150AND datasheet(79/111 Pages) PERICOM

79 / 111 page

PI7C8150A

2-PORT PCI-TO-PCI BRIDGE

Page 79 of 111

APRIL 2006 – Revision 1.1

Bit

Function

Type

Description

Parity Error

Response

R/W

Controls response to parity errors

0: PI7C8150A may ignore any parity errors that it detects and

continue normal operation

1: PI7C8150A must take its normal action when a parity error is

detected

Reset to 0

Wait Cycle

Control

R/O

Controls the ability to perform address / data stepping

0: disable address/data stepping (affects primary and secondary)

1: enable address/data stepping (affects primary and secondary)

Reset to 0

P_SERR_L

enable

R/W

Controls the enable for the P_SERR_L pin

0: disable the P_SERR_L driver

1: enable the P_SERR_L driver

Reset to 0

Fast Back-to-

Back Enable

R/W

Controls PI7C8150A’s ability to generate fast back-to-back

transactions to different devices on the primary interface.

0: no fast back-to-back transactions

1: enable fast back-to-back transactions

Reset to 0

15:10

Reserved

R/O

Returns 000000 when read

14.1.4

STATUS REGISTER – OFFSET 04h

Bit

Function

Type

Description

19:16

Reserved

R/O

Reset to 0

Capabilities List

R/O

Set to 1 to enable support for the capability list (offset 34h is the

pointer to the data structure)

Reset to 1

66MHz Capable

R/O

Set to 1 to enable 66MHz operation on the primary interface

Reset to 1

Reserved

R/O

Reset to 0

Fast Back-to-

Back Capable

R/O

Set to 1 to enable decoding of fast back-to-back transactions on the

primary interface to different targets

Reset to 1

Data Parity Error

Detected

R/WC

Set to 1 when P_PERR_L is asserted and bit 6 of command register

is set

Reset to 0

26:25

DEVSEL_L

timing

R/O

DEVSEL_L timing (medium decoding)

00: fast DEVSEL_L decoding

01: medium DEVSEL_L decoding

10: slow DEVSEL_L decoding

11: reserved

Reset to 01

06-0057

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