PI7C8150AND datasheet(72/111 Pages) PERICOM

72 / 111 page

PI7C8150A

2-PORT PCI-TO-PCI BRIDGE

Page 72 of 111

APRIL 2006 – Revision 1.1

connected to anything. The next bit is tied LOW because that secondary clock output is

connected to the PI7C8150A S_CLKIN input. When the secondary reset signal, S_RST_L,

is detected asserted and the primary reset signal, P_RST_L, is detected deasserted,

PI7C8150A drives GPIO[2] LOW for one cycle to load the clock mask inputs into the shift

This shifts the clock mask into MSK_IN; the most significant bit is shifted in first, and the

least significant bit is shifted in last.

After the shift operation is complete, PI7C8150A tri-states the GPIO signals and can

deassert S_RST_L if the secondary reset bit is clear. PI7C8150A then ignores MSK_IN.

Control of the GPIO signal now reverts to PI7C8150A GPIO control registers. The clock

disable mask can be modified subsequently through a configuration write command to the

secondary clock control register in device-specific configuration space.

10.3

LIVE INSERTION

The GPIO[3] pin can be used, along with a live insertion mode bit, to disable transaction

forwarding.

To enable live insertion mode, the live insertion mode bit in the chip control register must

be set to 1, and the output enable control for GPIO[3] must be set to input only in the GPIO

output enable control register. When live insertion mode is enabled, whenever GPIO[3] is

driven to a value of 1, the I/O enable, the memory enable, and the master enable bits are

internally masked to 0. This means that, as a target, PI7C8150A no longer accepts any I/O

or memory transactions, on either interface. When read, the register bits still reflect the

value originally written by a configuration write command; when GPIO[3] is deasserted,

the internal enable bits return to their original value (as they appear when read from the

command register). When this mode is enabled, as a master, PI7C8150A completes any

posted write or delayed request transactions that have already been queued.

Delayed completion transactions are not returned to the master in this mode because

PI7C8150A is not responding to any I/O or memory transactions during this time.

PI7C8150A continues to accept configuration transactions in live insertion mode. Once live

insertion mode brings PI7C8150A to a halt and queued transactions are completed, the

secondary reset bit in the bridge control register can be used to assert S_RST_L, if desired,

to reset and tri-state secondary bus devices, and to enable any live insertion hardware.

PCI POWER MANAGEMENT

PI7C8150A incorporates functionality that meets the requirements of the PCI Power

Management Specification, Revision 1.0. These features include:

PCI Power Management registers using the Enhanced Capabilities Port (ECP) address

mechanism

Support for D0, D3 hot and D3 cold power management states

Support for D0, D1, D2, D3 hot , and D3 cold power management states for devices

behind the bridge

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PI7C8150AND Datasheet(PDF) 72 Page - Pericom Semiconductor Corporation

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