PI7C8150AND datasheet(75/111 Pages) PERICOM

75 / 111 page

PI7C8150A

2-PORT PCI-TO-PCI BRIDGE

Page 75 of 111

APRIL 2006 – Revision 1.1

P_CBE [3:0]

Command

Action

0001

Special Cycle

Do not claim. Ignore.

0010

I/O Read

1. If address is within pass through I/O range, claim and pass

through.

2. Otherwise, do not pass through and do not claim for

internal access.

0011

I/O Write

Same as I/O Read.

0100

Reserved

-----

0101

Reserved

-----

0110

Memory Read

1. If address is within pass through memory range, claim and

pass through.

2. If address is within pass through memory mapped I/O

range, claim and pass through.

3. Otherwise, do not pass through and do not claim for

internal access.

0111

Memory Write

Same as Memory Read.

1000

Reserved

-----

1001

Reserved

-----

1010

Configuration Read

Type 0 Configuration Read:

If the bridge’s IDSEL line is asserted, perform function

decode and claim if target function is implemented.

Otherwise, ignore. If claimed, permit access to target

function’s configuration registers. Do not pass through

under any circumstances.

Type 1 Configuration Read:

1. If the target bus is the bridge’s secondary bus: claim and

pass through as a Type 0 Configuration Read.

2. If the target bus is a subordinate bus that exists behind the

bridge (but not equal to the secondary bus): claim and pass

through as a Type 1 Configuration Read.

3. Otherwise, ignore.

1011

Configuration Write

Type 0 Configuration Write: same as Configuration

Read.

Type 1 Configuration Write (not special cycle request):

1. If the target bus is the bridge’s secondary bus: claim and

pass through as a Type 0 Configuration Write

2. If the target bus is a subordinate bus that exists behind the

bridge (but not equal to the secondary bus): claim and pass

through unchanged as a Type 1 Configuration Write.

3. Otherwise, ignore.

Configuration Write as Special Cycle Request

(device = 1Fh, function = 7h)

1. If the target bus is the bridges secondary bus:

claim and pass through as a special cycle.

2. If the target bus is a subordinate bus that exists

behind the bridge (but not equal to the secondary

bus): claim and pass through unchanged as a type

1 Configuration Write.

3. Otherwise ignore

1100

Memory Read

Multiple

Same as Memory Read

1101

Dual Address Cycle

Supported

1110

Memory Read Line

Same as Memory Read

06-0057

PI7C8150AND Datasheet(PDF) 75 Page - Pericom Semiconductor Corporation

PI7C8150AND Datasheet(HTML) 75 Page - Pericom Semiconductor Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL