PI7C8150AND datasheet(63/111 Pages) PERICOM

63 / 111 page

PI7C8150A

2-PORT PCI-TO-PCI BRIDGE

Page 63 of 111

APRIL 2006 – Revision 1.1

Master timeout on delayed transaction

The device-specific P_SERR_L status register reports the reason for the assertion of

P_SERR_L. Most of these events have additional device-specific disable bits in the

P_SERR_L event disable register that make it possible to mask out P_SERR_L assertion

for specific events. The master timeout condition has a SERR_L enable bit for that event in

the bridge control register and therefore does not have a device-specific disable bit.

EXCLUSIVE ACCESS

This chapter describes the use of the LOCK_L signal to implement exclusive access to a

target for transactions that cross PI7C8150A.

7.1

CONCURRENT LOCKS

The primary and secondary bus lock mechanisms operate concurrently except when

a locked transaction crosses PI7C8150A. A primary master can lock a primary target

without affecting the status of the lock on the secondary bus, and vice versa. This means

that a primary master can lock a primary target at the same time that a secondary master

locks a secondary target.

7.2

ACQUIRING EXCLUSIVE ACCESS ACROSS PI7C8150A

For any PCI bus, before acquiring access to the LOCK_L signal and starting a series of

locked transactions, the initiator must first check that both of the following conditions are

met:

The PCI bus must be idle.

The LOCK_L signal must be de-asserted.

The initiator leaves the LOCK_L signal de-asserted during the address phase and asserts

LOCK_L one clock cycle later. Once a data transfer is completed from the target, the target

lock has been achieved.

7.2.1

LOCKED TRANSACTIONS IN DOWNSTREAM DIRECTION

Locked transactions can cross PI7C8150A only in the downstream direction, from the

primary bus to the secondary bus.

When the target resides on another PCI bus, the master must acquire not only the lock on

its own PCI bus but also the lock on every bus between its bus and the target’s bus. When

PI7C8150A detects on the primary bus, an initial locked transaction intended for a target

on the secondary bus, PI7C8150A samples the address, transaction type, byte enable bits,

and parity, as described in Section 3.5.4. It also samples the lock signal. If there is a lock

06-0057

PI7C8150AND Datasheet(PDF) 63 Page - Pericom Semiconductor Corporation