PI7C8150AND datasheet(6/111 Pages) PERICOM

6 / 111 page

PI7C8150A

2-PORT PCI-TO-PCI BRIDGE

Page 6 of 111

APRIL 2006 – Revision 1.1

3.8.4.2

TARGET DISCONNECT ................................................................................................ 40

3.8.4.3

TARGET ABORT ............................................................................................................ 40

ADDRESS DECODING....................................................................................... 41

4.1

ADDRESS RANGES ................................................................................................................... 41

4.2

I/O ADDRESS DECODING........................................................................................................ 41

4.2.1

I/O BASE AND LIMIT ADDRESS REGISTER................................................................ 42

4.2.2

ISA MODE........................................................................................................................... 43

4.3

MEMORY ADDRESS DECODING ........................................................................................... 43

4.3.1

MEMORY-MAPPED I/O BASE AND LIMIT ADDRESS REGISTERS ......................... 44

4.3.2

PREFETCHABLE MEMORY BASE AND LIMIT ADDRESS REGISTERS ................. 45

4.4

VGA SUPPORT ........................................................................................................................... 46

4.4.1

VGA MODE ......................................................................................................................... 46

4.4.2

VGA SNOOP MODE........................................................................................................... 46

TRANSACTION ORDERING ............................................................................ 47

5.1

TRANSACTIONS GOVERNED BY ORDERING RULES ....................................................... 47

5.2

GENERAL ORDERING GUIDELINES ..................................................................................... 48

5.3

ORDERING RULES.................................................................................................................... 48

5.4

DATA SYNCHRONIZATION .................................................................................................... 51

ERROR HANDLING ........................................................................................... 52

6.1

ADDRESS PARITY ERRORS .................................................................................................... 52

6.2

DATA PARITY ERRORS ........................................................................................................... 53

6.2.1

CONFIGURATION WRITE TRANSACTIONS TO CONFIGURATION SPACE.......... 53

6.2.2

READ TRANSACTIONS .................................................................................................... 53

6.2.3

DELAYED WRITE TRANSACTIONS............................................................................... 54

6.2.4

POSTED WRITE TRANSACTIONS.................................................................................. 57

6.3

DATA PARITY ERROR REPORTING SUMMARY................................................................. 58

6.4

SYSTEM ERROR (SERR_L) REPORTING............................................................................... 62

EXCLUSIVE ACCESS ........................................................................................ 63

7.1

CONCURRENT LOCKS ............................................................................................................. 63

7.2

ACQUIRING EXCLUSIVE ACCESS ACROSS PI7C8150A .................................................... 63

7.2.1

LOCKED TRANSACTIONS IN DOWNSTREAM DIRECTION ..................................... 63

7.2.2

LOCKED TRANSACTION IN UPSTREAM DIRECTION .............................................. 65

7.3

ENDING EXCLUSIVE ACCESS................................................................................................ 65

PCI BUS ARBITRATION ................................................................................... 66

8.1

PRIMARY PCI BUS ARBITRATION ........................................................................................ 66

8.2

SECONDARY PCI BUS ARBITRATION .................................................................................. 66

8.2.1

SECONDARY BUS ARBITRATION USING THE INTERNAL ARBITER.................... 66

8.2.2

PREEMPTION .................................................................................................................... 68

8.2.3

SECONDARY BUS ARBITRATION USING AN EXTERNAL ARBITER...................... 68

8.2.4

BUS PARKING.................................................................................................................... 68

CLOCKS................................................................................................................ 69

9.1

PRIMARY CLOCK INPUTS....................................................................................................... 69

9.2

SECONDARY CLOCK OUTPUTS ............................................................................................ 69

GENERAL PURPOSE I/O INTERFACE.......................................................... 69

06-0057

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