| Electronic Components Datasheet Search |
|
PI7C8150AND Datasheet(PDF) 37 Page - Pericom Semiconductor Corporation |
|
|
|||||||||||||||||||||||||||||
PI7C8150AND Datasheet(HTML) 37 Page - Pericom Semiconductor Corporation |
|
37 / 111 page ![]() PI7C8150A 2-PORT PCI-TO-PCI BRIDGE Page 37 of 111 APRIL 2006 – Revision 1.1 Target disconnect Target abort PI7C8150A handles these terminations in different ways, depending on the type of transaction being performed. 3.8.3.1 DELAYED WRITE TARGET TERMINATION RESPONSE When PI7C8150A initiates a delayed write transaction, the type of target termination received from the target can be passed back to the initiator. Table 3-7 shows the response to each type of target termination that occurs during a delayed write transaction. PI7C8150A repeats a delayed write transaction until one of the following conditions is met: PI7C8150A completes at least one data transfer. PI7C8150A receives a master abort. PI7C8150A receives a target abort. PI7C8150A makes 2 24 (default) or 232 (maximum) write attempts resulting in a response of target retry. Table 3-7. Delayed Write Target Termination Response Target Termination Response Normal Returning disconnect to initiator with first data transfer only if multiple data phases requested. Target Retry Returning target retry to initiator. Continue write attempts to target Target Disconnect Returning disconnect to initiator with first data transfer only if multiple data phases requested. Target Abort Returning target abort to initiator. Set received target abort bit in target interface status register. Set signaled target abort bit in initiator interface status register. After the PI7C8150A makes 2 24 (default) attempts of the same delayed write trans-action on the target bus, PI7C8150A asserts P_SERR_L if the SERR_L enable bit (bit 8 of command register for the secondary bus) is set and the delayed-write-non-delivery bit is not set. The delayed-write-non-delivery bit is bit 5 of P_SERR_L event disable register (offset 64h). PI7C8150A will report system error. See Section 6.4 for a description of system error conditions. 3.8.3.2 POSTED WRITE TARGET TERMINATION RESPONSE When PI7C8150A initiates a posted write transaction, the target termination cannot be passed back to the initiator. Table 3-8 shows the response to each type of target termination that occurs during a posted write transaction. 06-0057 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |