PI7C8150AND datasheet(74/111 Pages) PERICOM

74 / 111 page

PI7C8150A

2-PORT PCI-TO-PCI BRIDGE

Page 74 of 111

APRIL 2006 – Revision 1.1

12.2

SECONDARY INTERFACE RESET

PI7C8150A is responsible for driving the secondary bus reset signals, S_RESET_L.

PI7C8150A asserts S_RESET_L when any of the following conditions are met:

Signal P_RESET_L is asserted. Signal S_RESET_L remains asserted as long as

P_RESET_L is asserted and does not de-assert until P_RESET_L is de-asserted.

The secondary reset bit in the bridge control register is set. Signal S_RESET_L

remains asserted until a configuration write operation clears the secondary reset bit.

S_RESET_L pin is asserted. When S_RESET_L is asserted, PI7C8150A immediately 3-

states all the secondary PCI interface signals associated with the secondary port. The

S_RESET_L in asserting and de-asserting edges can be asynchronous to P_CLK.

When S_RESET_L is asserted, all secondary PCI interface control signals, including the

secondary grant outputs, are immediately 3-stated. Signals S1_AD, S1_CBE[3:0]#, S_PAR

are driven low for the duration of S_RESET_L assertion. All posted write and delayed

transaction data buffers are reset. Therefore, any transactions residing inside the buffers at

the time of secondary reset are discarded.

When S_RESET_L is asserted by means of the secondary reset bit, PI7C8150A remains

accessible during secondary interface reset and continues to respond to accesses to its

configuration space from the primary interface.

12.3

CHIP RESET

The chip reset bit in the diagnostic control register can be used to reset the PI7C8150A and

the secondary bus.

When the chip reset bit is set, all registers and chip state are reset and all signals are

tristated. S_RESET_L is asserted and the secondary reset bit is automatically set.

S_RESET_L remains asserted until a configuration write operation clears the secondary

reset bit and the serial clock mask has been shifted in. Within 20 PCI clock cycles after

completion of the configuration write operation, PI7C8150A’s reset bit automatically

clears and PI7C8150A is ready for configuration.

During reset, PI7C8150A is inaccessible.

SUPPORTED COMMANDS

The PCI command set is given below for the primary and secondary interfaces.

13.1

PRIMARY INTERFACE

P_CBE [3:0]

Command

Action

0000

Interrupt

Acknowledge

Ignore

06-0057

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