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PI7C8150AND Datasheet(PDF) 92 Page - Pericom Semiconductor Corporation |
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PI7C8150AND Datasheet(HTML) 92 Page - Pericom Semiconductor Corporation |
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92 / 111 page  PI7C8150A 2-PORT PCI-TO-PCI BRIDGE Page 92 of 111 APRIL 2006 – Revision 1.1 Bit Function Type Description 19:16 GPIO Output Enable Write-1- to-Clear R/WC Writing 1 to and of these bits configures the corresponding GPIO[3:0] pin as an input only. The output driver is tristated. Writing 0 to this register has no effect and will reflect the last value written when read. Reset to 0. 23:20 GPIO Output Enable Write-1- to-Set R/WS Writing 1 to and of these bits configures the corresponding GPIO[3:0] pin as bidirectional. The output driver is enabled and drives the value set in the output data register (65h). Writing 0 to this register has no effect and will reflect the last value written when read. Reset to 0. 27:24 Reserved R Reserved. Returns 0 when read. Reset to 0. 31:28 GPIO Input Data Register R/O Reads the state of the GPIO[3:0] pins. The state is updated on the PCI clock following a change in the GPIO[3:0] pins. 14.1.40 SECONDARY CLOCK CONTROL REGISTER – OFFSET 68h Bit Function Type Description 1:0 Clock 0 disable R/W If either bit is 0, then S_CLKOUT [0] is enabled. If both bits are 1, then S_CLKOUT [0] is disabled. 3:2 Clock 1 disable R/W If either bit is 0, then S_CLKOUT [1] is enabled. If both bits are 1, then S_CLKOUT [1] is disabled. 5:4 Clock 2 disable R/W If either bit is 0, then S_CLKOUT [2] is enabled. If both bits are 1, then S_CLKOUT [2] is disabled. 7:6 Clock 3 disable R/W If either bit is 0, then S_CLKOUT [3] is enabled. If both bits are 1, then S_CLKOUT [3] is disabled. 8 Clock 4 disable R/W If bit is 0, then S_CLKOUT [4] is enabled. If bit is 1, then S_CLKOUT [4] is disabled and driven low. 9 Clock 5 disable R/W If bit is 0, then S_CLKOUT [5] is enabled. If bit is 1, then S_CLKOUT [5] is disabled and driven low. 10 Clock 6 disable R/W If bit is 0, then S_CLKOUT [6] is enabled. If bit is 1, then S_CLKOUT [6] is disabled and driven low. 11 Clock 7 disable R/W If bit is 0, then S_CLKOUT [7] is enabled. If bit is 1, then S_CLKOUT [7] is disabled and driven low. 12 Clock 8 disable R/W If bit is 0, then S_CLKOUT [8] is enabled. If bit is 1, then S_CLKOUT [8] is disabled and driven low. 13 Clock 9 disable R/W If bit is 0, then S_CLKOUT [9] is enabled. If bit is 1, then S_CLKOUT [9] is disabled and driven low. 15:14 Reserved RO Reserved. Returns 00 when read. 14.1.41 P_SERR_L STATUS REGISTER – OFFSET 68h Bit Function Type Description 16 Address Parity Error R/WC 1: Signal P_SERR_L was asserted because an address parity error was detected on P or S bus. Reset to 0 17 Posted Write Data Parity Error R/WC 1: Signal P_SERR_L was asserted because a posted write data parity error was detected on the target bus. Reset to 0 18 Posted Write Non-delivery R/WC 1: Signal P_SERR_L was asserted because the bridge was unable to deliver post memory write data to the target after 2 24 attempts. Reset to 0 06-0057 |
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