ATAM862 datasheet(20/110 Pages) ATMEL

20 / 110 page

4554E–4BMCU–05/06

ATAM862-3

16.7

Interrupt Structure

The microcontroller can handle interrupts with eight different priority levels. They can be gener-

ated from the internal and external interrupt sources or by a software interrupt from the CPU

itself. Each interrupt level has a hard-wired priority and an associated vector for the service rou-

tine in the EEPROM (see Table 16-1 on page 21). The programmer can postpone the

processing of interrupts by resetting the interrupt enable flag (I) in the CCR. An interrupt occur-

rence will still be registered, but the interrupt routine only started after the I-flag is set. All

interrupts can be masked, and the priority individually software configured by programming the

appropriate control register of the interrupting module (see section “Peripheral Modules” on

page 32).

16.7.1

Interrupt Processing

For processing the eight interrupt levels, the microcontroller includes an interrupt controller with

two 8-bit wide interrupt pending and interrupt active registers. The interrupt controller samples all

interrupt requests during every non-I/O instruction cycle and latches these in the interrupt pend-

ing register. If no higher priority interrupt is present in the interrupt active register, it signals the

CPU to interrupt the current program execution. If the interrupt enable bit is set, the processor

enters an interrupt acknowledge cycle. During this cycle a short call (SCALL) instruction to the

service routine is executed and the current PC is saved on the return stack. An interrupt service

routine is completed with the RTI instruction. This instruction resets the corresponding bits in the

interrupt pending/active register and fetches the return address from the return stack to the pro-

gram counter. When the interrupt enable flag is reset (triggering of interrupt routines is disabled),

the execution of new interrupt service routines is inhibited but not the logging of the interrupt

requests in the interrupt pending register. The execution of the interrupt is delayed until the inter-

rupt enable flag is set again. Note that interrupts are only lost if an interrupt request occurs while

the corresponding bit in the pending register is still set (i.e., the interrupt service routine is not yet

finished).

It should be noted that automatic stacking of the RBR is not carried out by the hardware and so

if ROM banking is used, the RBR must be stacked on the expression stack by the application

program and restored before the RTI. After a master reset (power-on, brown-out or watchdog

reset), the interrupt enable flag and the interrupt pending and interrupt active register are all

reset.

16.7.2

Interrupt Latency

The interrupt latency is the time from the occurrence of the interrupt to the interrupt service rou-

tine being activated. This is extremely short (taking between 3 to 5 machine cycles depending

on the state of the core).

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