ATAM862 datasheet(58/110 Pages) ATMEL

58 / 110 page

4554E–4BMCU–05/06

ATAM862-3

23. Timer 3

23.1

Features

• Two Compare Registers

• Capture Register

• Edge Sensitive Input with Zero Cross Detection Capability

• Trigger and Single Action Modes

• Output Control Modes

• Automatically Modulation and Demodulation Modes

• FSK Modulation

• Pulse width Modulation (PWM)

• Manchester Demodulation Together with SSI

• Biphase Demodulation Together with SSI

• Pulse-width Demodulation Together with SSI

Figure 23-1. Timer 3

Timer 3 consists of an 8-bit up-counter with two compare registers and one capture register. The

timer can be used as event counter, timer and signal generator. Its output can be programmed

as modulator and demodulator for the serial interface. The two compare registers enable various

modes of signal generation, modulation and demodulation. The counter can be driven by inter-

nal and external clock sources. For external clock sources, it has a programmable

edge-sensitive input which can be used as counter input, capture signal input or trigger input.

This timer input is synchronized with SYSCL. Therefore, in the power-down mode SLEEP (CPU

core -> sleep and OSC-Stop -> yes), this timer input is stopped too. The counter is readable via

its capture register while it is running. In capture mode, the counter value can be captured by a

programmable capture event from the Timer 3 input or Timer 2 output.

8-bit comparator

Compare register 1

RES

Capture register

8-bit counter

Compare register 2

Control

C31

C32

Control

T3SM1

T3RM1

T3IM1

T3TM1

TOG2

T3I

T3TM2

T3IM2

T3RM2

T3SM2

CL3

T3EIM

TOG3

INT5

CM31

CM32

: T3M1

: T3M2

ATAM862 Datasheet(PDF) 58 Page - ATMEL Corporation

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