ATAM862 datasheet(64/110 Pages) ATMEL

64 / 110 page

4554E–4BMCU–05/06

ATAM862-3

23.3.4

Timer 3 – Mode 9: Pulse-width Modulation with the Shift Register

The two compare registers are used for generating two different time intervals. The SSI internal

data output (SO) selects which compare register is used for the output pulse generation. In this

mode both compare- and compare-mode registers must be programmed for generating the two

pulse widths. It is also useful to enable the single-action mode for extreme duty cycles. Timer 2

is used as baudrate generator and for the trigger restart of Timer 3. The SSI must be supplied

with a toggle signal of Timer 2. The counter is driven by an internal or external clock source (see

“Combination Mode 7: Pulse-width Modulation (PWM)” on page 88).

Figure 23-9. Pulse-width Modulation

23.3.5

Timer 3 – Mode 10: Manchester Demodulation/Pulse-width Demodulation

For Manchester demodulation, the edge detection stage must be programmed to detect each

edge at the input. These edges are evaluated by the demodulator stage. The timer stage is used

to generate the shift clock for the SSI. The compare register 1 match event defines the correct

moment for shifting the state from the input T3I as the decoded bit into shift register - after that

the demodulator waits for the next edge to synchronize the timer by a reset for the next bit. The

compare register 2 can also be used to detect a time-out error and handle it with an interrupt

routine (see “Combination Mode 8: Manchester Demodulation/Pulse-width Demodulation” on

page 89).

Figure 23-10. Manchester Demodulation

000 0 0 00 00

000 0

Counter 3

CM31

CM32

T3O

00 0 001 234 56 7 8 9 1011121314150 12 345

TOG2

67 8

91112

2 3

SIR

SCO

T3R

0111

BIT 0

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

Synchronize

Manchester demodulation mode

Timer 3

mode

T3EX

SR-DATA

T3I

CM31=SCI

ATAM862 Datasheet(PDF) 64 Page - ATMEL Corporation

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