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EP1M350 Datasheet(PDF) 48 Page - Altera Corporation

Part # EP1M350
Description  Programmable Logic Device Family
PDF  86 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP1M350 Datasheet(HTML) 48 Page - Altera Corporation

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Altera Corporation
Mercury Programmable Logic Device Family Data Sheet
The Mercury IOE includes programmable delays that can be activated to
ensure zero hold times, minimum clock-to-output times, input IOE
register-to-core register transfers, or core-to-output IOE register transfers.
A path in which a pin directly drives a register may require the delay to
ensure zero hold time, whereas a path in which a pin drives a register
through combinatorial logic may not require the delay. Programmable
delays exist for decreasing input pin to core and IOE input register delays.
The Quartus II Compiler can program these delays automatically to
minimize setup time while providing a zero hold time. Delays are also
programmable for increasing the register to pin delays for output and/or
output enable registers. A programmable delay exists for increasing the
tZX delay to the output pin, which is required for ZBT interfaces. Table 10
shows the programmable delays for Mercury devices.
Note to Table 10:
(1)
This delay has four settings: off and three levels of delay.
The IOE registers in Mercury devices share the same source for clear or
preset. Use of the preset/clear is programmable for each individual IOE.
The register(s) can be programmed to power up high or low after
configuration is complete. If programmed to power up low, an
asynchronous clear can control the register(s). If programmed to power
up high, an asynchronous preset can control the register(s). This feature
prevents the inadvertent activation of another device’s active-low input
upon power-up. Figure 26 shows the IOE for Mercury devices.
Table 10. Mercury Programmable Delay Chain
Programmable Delays
Quartus II Logic Option
Input pin to core delay (1)
Decrease input delay to internal cells
Input pin to input register delay
Decrease input delay to input register
Output propagation delay
Increase delay to output pin
Output enable register tCO delay
Increase delay to OE pin
Output tZX delay
Increase tZX delay to output pin



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