EP1M350 datasheet(49/86 Pages) ALTERA

49 / 86 page

Altera Corporation

Mercury Programmable Logic Device Family Data Sheet

Figure 26. Mercury IOE

Note to Figure 26:

(1)

This programmable delay has four settings: off and three levels of delay.

Double Data Rate I/O

Mercury device’s have three register IOEs to support the DDRIO feature,

which makes double data rate interfaces possible by clocking data on both

positive and negative clock edges. The IOE in Mercury devices supports

double data rate input and double data rate output modes.

CLRN/PRN

ENA

Chip-Wide Reset

OE Register

CLRN/PRN

ENA

CLRN/PRN

ENA

Output Register

Input Register

Output tZX

Delay

OE Register

tCO Delay

Output

Propagation Delay

Input Pin to

Core Delay (1)

Drive Strength Control

Open-Drain Output

Slew Control

Input Pin to Input

VCCIO

Optional

PCI Clamp

Programmable

Pull-Up

Priority Row Interconnect (for Associated LAB Row)

Row Interconnect (for Associated LAB Row)

Column and

Priority

Column

Interconnect

Associated LAB

Local Interconnect

Two Row

Local Fast

Signals

Six Fast

Global

Signals

Four

Dedicated

Clocks

Bus-Hold

Circuit

EP1M350 Datasheet(PDF) 49 Page - Altera Corporation

EP1M350 Datasheet(HTML) 49 Page - Altera Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86

Datasheet Download

Link URL