EP1M350 datasheet(52/86 Pages) ALTERA

52 / 86 page

Altera Corporation

Mercury Programmable Logic Device Family Data Sheet

Zero Bus Turnaround SRAM Interface Support

In addition to DDR SDRAM support, Mercury device I/O pins also

support interfacing with ZBT SRAM blocks at up to 200 MHz. ZBT SRAM

blocks are designed to eliminate dead bus cycles when turning a

bidirectional bus around between reads and writes, or writes and reads.

ZBT allows for 100% bus utilization because ZBT SRAM can read or write

on every clock cycle.

To avoid bus contention, the output tZX delay ensures that the clock-to-

low-impedance time (tZX) is greater than the clock-to-high-impedance

time (tXZ). Time delay control of clocks to the OE/output and input

meet ZBT tCO and tSU times.

Programmable Drive Strength

The output buffer for each Mercury device I/O pin has a programmable

drive strength control for certain I/O standards. The LVTTL standard has

several levels of drive strength that can be controlled by the user. SSTL-3

class I and II, SSTL-2 class I and II, HSTL class I and II, and 3.3-V GTL+

support a minimum or maximum setting. The minimum setting is the

lowest drive strength that guarantees the IOH/IOL of the standard. The

maximum setting provides higher drive strength that allows for faster

switching and is the default setting. Using settings below the maximum

provides signal slew-rate control to reduce system noise and signal

overshoot. Table 11 shows the possible settings for the I/O standards with

drive strength control.

EP1M350 Datasheet(PDF) 52 Page - Altera Corporation