EP1M350 datasheet(34/86 Pages) ALTERA

34 / 86 page

Altera Corporation

Mercury Programmable Logic Device Family Data Sheet

Table 9 summarizes how various elements of the Mercury architecture

drive each other.

Notes to Table 9:

(1)

This direct connection is possible through the FastLUT connection.

(2)

IOEs can connect to the adjacent LAB’s local interconnects in the associated LAB row.

(3)

IOEs can connect to row and priority row interconnects in the associated LAB row.

(4)

This connection is used for multiplier mode.

Embedded

System Block

The ESB can implement various types of memory blocks, including quad-

port, true dual-port, dual- and single-port RAM, ROM, FIFO, and CAM

blocks.

The ESB includes input and output registers; the input registers

synchronize reads and/or writes, and the output registers can pipeline

designs to further increase system performance. The ESB offers a quad

port mode, which supports up to four port operations, two reads and two

writes simultaneously, with the ability for a different clock on each of the

four ports. Figure 17 shows the ESB quad-port block diagram.

Table 9. Mercury Routing Scheme

Source

Destination

Local

Interconnect

IOE

ESB Row

Interconnect

ESB

Row

Priority

Row

RapidLAB

Interconnect

Column

Priority

Column

Leap

Lines

(1)

vvv

Local

Interconnect

IOE

v (2)

(3)

v (3)

ESB Row

Interconnect

ESB

Row

Priority Row

RapidLAB

Interconnect

(4)

Column

Priority

Column

vvv

Leap Lines

vvv

EP1M350 Datasheet(PDF) 34 Page - Altera Corporation

EP1M350 Datasheet(HTML) 34 Page - Altera Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86

Datasheet Download

Link URL