EP1M350 datasheet(58/86 Pages) ALTERA

58 / 86 page

Altera Corporation

Mercury Programmable Logic Device Family Data Sheet

For the HSDI I/O band, half of the dedicated banks support LVDS, 3.3-V

PCML or LVPECL, and receiver inputs, while the other half support

LVDS, PCML or LVPECL, and transmitter outputs. A single device can

support 1.5-V, 1.8-V, 2.5-V, and 3.3-V interfaces; each bank can support a

VCCIO standard independently. Each bank can also use a separate VREF

level so that each bank can support any of the terminated standards (such

as SSTL-3) independently. A bank can support a single VREF level. Each

bank contains a fixed VREF pin for voltage referenced standards. This pin

can be used as a regular I/O if a VREF standard is not used. Table 13 shows

the number of I/O banks in each Mercury device.

Each bank can support multiple standards with the same VCCIO for output

pins. For EP1M120 devices, each bank can support one voltage-referenced

I/O standard, but can support multiple I/O standards with the same

VCCIO and VREF voltage levels. For example, when VCCIO is 3.3 V, a bank

can support LVTTL, LVCMOS, 3.3-V PCI, and SSTL-3 for inputs and

outputs. Figure 30 shows the I/O bank layout for an EP1M120 device. For

EP1M350 devices, each bank can support two voltage-reverenced I/O

standards; each I/O bank is split into two voltage-referenced sub-banks.

When using the two HSDI transmitter banks as regular I/O banks in a

non-HSDI mode, those two banks require the same VCCIO level. However,

each HSDI transmitter bank supports its own VREF level.

Table 13. Number of I/O Banks per Device

Device

Regular I/O Banks

HSDI Band I/O Banks

EP1M120

EP1M350

EP1M350 Datasheet(PDF) 58 Page - Altera Corporation