EP1M350 datasheet(9/86 Pages) ALTERA

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Altera Corporation

Mercury Programmable Logic Device Family Data Sheet

In source-synchronous mode, source synchronous interfacing is

supported at up to 840 Mbps. Serial channels are transmitted and received

along with a low speed clock. The receiving device then multiplies the

clock by a factor of 1 to 12, 14, 16, 18, or 20. The serialization/

deserialization rate can be any number from 4, 7, 8, 9 to 12, 14, 16, 18, or 20

and does not have to equal the clock multiplication value. For example, an

840-Mbps LVDS channel can be received along with a 84-MHz clock. The

84-MHz clock is multiplied by 10 to drive the serial shift register, but the

20-bits wide at 42 to 120 MHz. See Figures 2 and 3.

Figure 2. Receiver Diagram for Source Synchronous Mode

Notes (1), (2)

Notes to Figure 2:

(1)

EP1M350 devices have 18 individual receiver channels. EP1M120 devices have 8 individual receiver channels.

(2)

W = 1 to 12, 14, 16, 18, or 20

J = 4, 7, 8, 9 to 12, 14, 16, 18, or 20

W does not have to equal J.

(3)

This clock pin drives an HSDI PLL only. It does not drive to the core.

—

Receiver

Channel

—

Receiver

Channel

—

Receiver

Channel

HSDI_CLK2 (3)

HSDI

PLL2

×W

Deserializer

Data to

LEs

To Global

Clock

Receiver Channel 1

Receiver Channel 8

Receiver Channel 2

J Bits Wide

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