EP1M350 datasheet(63/86 Pages) ALTERA

63 / 86 page

Altera Corporation

Mercury Programmable Logic Device Family Data Sheet

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Normal Mode: The external clock output pin will have phase delay

relative to the clock input pin. If an internal clock is used in this mode,

the IOE register clock will be phase aligned to the input clock pin.

Multiplication is allowed with the normal mode.

Advanced ClockShift Circuitry

General purpose PLLs in Mercury devices have advanced ClockShiftTM

circuitry that provides programmable phase shift and fine tune time delay

shift. For phase shifting, users can enter a phase shift (in degrees or time

units) that affects all PLL outputs. Phase shifts of 90, 180, and 270 can be

implemented exactly. Other values of phase shifting, or delay shifting in

time units, are allowed with a resolution range of 0.3 ns to 1.0 ns. This

resolution varies with frequency input and the user-entered

multiplication and division factors. The phase shift ability is only possible

on a multiplied or divided clock if the input and output frequency have

an integer multiple relationship (i.e., fIN/fOUT or fOUT/fIN must be an

integer).

In addition to the phase shift feature that affects all outputs, there is an

advanced fine time delay shift control on each of the four PLL outputs.

Each PLL output can be shifted in 250-ps increments for a range of –2.0 ns

to +2.0 ns. This ability can be used in conjunction with the phase shifting

ability that affects all outputs. fIN/fOUT does not need to have an integer

relationship for the advanced fine time delay shift control.

Clock Enable Signal

Mercury PLLs have a CLKLK_ENA pin for enabling/disabling all of the

device PLLs. When the CLKLK_ENA pin is high, the PLL drives a clock to

all its output ports. When the CLKLK_ENA pin is low, the clock0,

clock1

, clock2 and extclock ports are driven by GND and all of the

PLLs go out of lock. When the CLKLK_ENA pin goes high again, the PLL

must relock.

The individual enable port for each general purpose PLL is

programmable. If more than one general-purpose PLL is instantiated,

each one does not have to use the clock enable. To enable/disable the

device PLLs with the CLKLK_ENA pin, the inclocken port on the

altclklock

instance must be connected to the CLKLK_ENA input pin.

EP1M350 Datasheet(PDF) 63 Page - Altera Corporation