EP1M350 datasheet(8/86 Pages) ALTERA

8 / 86 page

Altera Corporation

Mercury Programmable Logic Device Family Data Sheet

Mercury devices provide four dedicated clock input pins and six

dedicated fast I/O pins that globally drive register control inputs,

including clocks. These signals ensure efficient distribution of high-speed,

low-skew control signals. The control signals use dedicated routing

channels to provide short delays and low skew. The dedicated fast signals

can also be driven by internal logic, providing an ideal solution for a clock

divider or internally generated asynchronous control signal with high

fan-out. The dedicated clock and fast I/O pins on Mercury devices can

also feed logic. Dedicated clocks can also be used with the Mercury

general purpose PLLs for clock management.

Each I/O row band also provides two additional I/O pins that can drive

two row-global signals. Row-global signals can drive register control

inputs for the LAB row associated with that particular I/O row band.

High-Speed

Differential

Interface

The top I/O or HSDI band in Mercury devices contains dedicated

circuitry for supporting differential standards at speeds up to 1.25 Gbps.

Mercury devices have dedicated differential buffers and circuitry to

support LVDS, LVPECL, and 3.3-V PCML I/O standards. Two dedicated

high-speed PLLs (separate from the general purpose PLLs) multiply

reference clocks and drive high-speed differential serializer/deserializer

channels. In addition, clock recovery units (CRUs) at each receiver

channel enable CDR. EP1M120 devices support eight input channels,

eight output channels, and two dedicated clock inputs for feeding the

receiver and/or transmitter PLLs. EP1M350 devices support 18 input

channels, 18 output channels, and two dedicated clock inputs.

Mercury devices have optional built-in 100-

Ω termination resistors on

HSDI differential receiver data pins and the HSDI_CLK1 and HSDI_CLK2

pins.

Designers can use the HSDI circuitry for the following applications:

■

Gigabit Ethernet backplanes

■

ATM, SONET

■

RapidIO

■

POS-PHY Level 4

■

Fibre Channel

■

SDTV

The HSDI band supports one of two possible modes:

■

Source-synchronous mode

■

Clock data recovery (CDR) mode

EP1M350 Datasheet(PDF) 8 Page - Altera Corporation

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