EP1M350 datasheet(11/86 Pages) ALTERA

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Altera Corporation

Mercury Programmable Logic Device Family Data Sheet

Table 6 defines the support for source-synchronous mode applications.

Note to Table 6:

(1)

You can use the CDR circuit to achieve data rates for DC coupled LVDS

applications. You must AC-couple the clock to a 2.2-V common mode voltage

(VCM) using the AC-coupling schemes in AN 134: Using Programmable I/O Standards

in Mercury Devices. The data channels should be DC-coupled. The byte alignment

relative to the clock is lost when using the CDR circuit. Therefore, a byte-alignment

circuit is required. Most Mercury source-synchronous designs already include

byte-alignment logic since they usually use DDR or SDR clocks. The CDR run

length requirement is waived if the reference clock and the receiver data come from

the same source and have the same frequency.

In CDR mode, serial data is supported up to 1.25 Gbps per channel. The

system provides a reference clock which is multiplied by the receiver or

transmitter PLL to the same rate as the data is provided. For the receiver,

this multiplied reference clock is used by a CRU on each receiver channel

to generate a recovered clock in-phase with the received data. That

recovered clock drives the programmable deserializer and synchronizer.

The synchronizer is a FIFO for data transfer between the recovered clock

domain and the global clock domain. The dedicated synchronizers can be

bypassed if necessary. For every receiver channel in the EP1M350 and

EP1M120 devices, the ÷J recovered clock can drive a priority column line

for use as a clock. See Figure 4.

Table 6. Source-Synchronous Mode

Data Rate

I/O Standard

LVDS

LVPECL

3.3-V PCML

≤ 840 Mbps

(1)

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