EP1M350 datasheet(25/86 Pages) ALTERA

25 / 86 page

Altera Corporation

Mercury Programmable Logic Device Family Data Sheet

Figure 11. Multiplier Mode LE

Notes to Figure 11:

(1)

LABCLKENA1

cannot be used in multiplier mode.

(2)

When the RapidLAB output is used, local interconnect outputs are unavailable.

The basis for the high-speed 16

× 16-bit multiplier in a Mercury device is

the binary tree multiplier. In the first stage of the binary tree, the

multiplicand bits, a[15:0], and the multiplier bits, b[15:0], are

multiplied together. The results of the first stage are sixteen 16-bit partial

products, a[15:0]b[15], a[15:0]b[14], . . . a[15:0]b[0]. The

partial products are then grouped into pairs and added together in the

second stage. In a similar fashion, the results of the previous stage are

grouped in pairs and then added forming the binary tree structure seen in

Figure 12.

LAB Carry-In

Carry-In0

Carry-In1

Carry-Out0

Carry-Out1

LAB Carry-Out

CLRN

ENA

Registered

Sum Output

Combinatorial

Sum Output

Combinatorial

Sum Output

Programmable

Inverter

Programmable

Inverter

M + 1

Programmable

Inverter

Programmable

Inverter

N + 1

Full

Adder

LAB-Wide Clock

Enable Signals (1)

Partial Product

Generation

RapidLAB

Interconnect (2)

LE Output

EP1M350 Datasheet(PDF) 25 Page - Altera Corporation

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