EP1M350 datasheet(22/86 Pages) ALTERA

22 / 86 page

Altera Corporation

Mercury Programmable Logic Device Family Data Sheet

The CSLA chain’s speed advantage results from the parallel pre-

computation of carry chains. Instead of including every LUT in the critical

path, only the propagation delays between LAB carry-in generation

circuits (LE 4 and LE 10) make up the critical path. This feature allows the

Mercury architecture to implement high-speed counters, adders,

multipliers, parity functions, and comparators of arbitrary width.

Figure 10 shows the CSLA circuitry in a LAB for a 10-bit full adder. One

portion of the LUT generates the sum of two bits using the input signals

and the appropriate carry-in bit; the sum is routed to the output of the LE.

The register can be bypassed for simple adders or used for accumulator

functions. Another portion of the LUT generates carry-out bits. A lab-

wide carry-in bit selects which chain is used for the addition of given

inputs. The actual carry-in signal for that selected chain, carry-in0 or

carry-in1

, selects the carry-out to carry forward, which is routed to the

carry-in signal of the next-higher-order bit. The final carry-out signal is

routed to an LE, where it is driven to local, row, or column interconnects.

EP1M350 Datasheet(PDF) 22 Page - Altera Corporation