EP1M350 datasheet(61/86 Pages) ALTERA

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Altera Corporation

Mercury Programmable Logic Device Family Data Sheet

General

Purpose PLL

Mercury devices have ClockLockTM, ClockBoostTM, and advanced

ClockShiftTM features, which use up to four general-purpose PLLs

(separate from the two HSDI PLLs) to province clock management and

clock-frequency synthesis. EP1M120 devices contain two general purpose

PLLs; EP1M350 devices contain four general purpose PLLs. These PLLs

allow designers to increase performance and provide clock-frequency

synthesis. The PLL reduces the clock delay within a device. This reduction

minimizes clock-to-output and setup times while maintaining zero hold

times. The PLLs, which provide programmable multiplication, allow the

designer to distribute a low-speed clock and multiply that clock on-

device. Mercury devices include a high-speed clock tree: unlike ASICs, the

user does not have to design and optimize the clock tree. The PLLs work

in conjunction with the Mercury device’s high-speed clock to provide

significant improvements in system performance and bandwidth.

Table 15 shows the general purpose PLL features for Mercury devices.

Figure 31 shows a Mercury PLL.

Note to Table 15:

(1)

n represents the prescale divider for the PLL input. k, p, q, and v represent the different post scale dividers for the

four possible PLL outputs. m, k, p, and q are integers that range from 1 to 160. n and v are integers that can range

from 1 to 16.

Figure 31. Mercury General-Purpose PLL

Table 15. Mercury General Purpose PLL Features

Device

Number of PLLs

ClockBoost

Feature (1)

Number of External

Clock Outputs

Number of

Feedback Inputs

Advanced

ClockShift

EP1M120

m/(n

× k, p, q, v)

EP1M350

m/(n

× k, p, q, v)4

Time

Delay/Shift

Time

Delay/Shift

Time

Delay/Shift

Time

Delay/Shift

Phase

Comparator

Voltage-Controlled

Oscillator

inclock

fbin

clock1

clock0

clock2

clock_ext

ClockLock

Phase Shift

Circuitry

EP1M350 Datasheet(PDF) 61 Page - Altera Corporation

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