EP1M350 datasheet(56/86 Pages) ALTERA

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Altera Corporation

Mercury Programmable Logic Device Family Data Sheet

Dedicated Fast Lines & I/O Pins

Mercury devices incorporate dedicated bidirectional pins for signals with

high internal fanout, such as PCI control signals. These pins are called

dedicated fast I/O pins (FAST1, FAST2, FAST3, FAST4, FAST5, and

FAST6

) and can drive the six global fast lines throughout the device, ideal

for fast clock, clock enable, clear, preset, or high fanout logic signal

distribution. The dedicated fast I/O pins have the same IOE as a regular

I/O pin. The dedicated fast lines can also be driven by a LE local

interconnect to generate internal global signals.

In addition to the device global fast lines, each LAB row has two dedicated

fast lines local to the row. This is ideal for high fanout control signals for

a section of a design that may fit into a single LAB row. Each I/O band

(with the exception of the top I/O band) has two dedicated row-global

fast I/O pins to drive the row-global fast resources for the associated LAB.

The dedicated local fast I/O pins have the same IOE as a regular I/O pin.

The LE local interconnect can drive dedicated row-global fast lines to

generate internal global signals specific to a row. There are no pin

connections for buried LAB rows; LE local interconnects drive the row-

global signals in those rows.

I/O Standard Support

Mercury device IOEs support the following I/O standards:

■

LVTTL

■

LVCMOS

■

1.8-V

■

2.5-V

■

3.3-V PCI

■

3.3-V PCI-X

■

3.3-V AGP (1

×, 2×)

■

LVDS

■

LVPECL

■

3.3-V PCML

■

GTL+

■

HSTL class I and II

■

SSTL-3 class I and II

■

SSTL-2 class I and II

■

CTT

EP1M350 Datasheet(PDF) 56 Page - Altera Corporation

EP1M350 Datasheet(HTML) 56 Page - Altera Corporation

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